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LTC4282 Datasheet(PDF) 29 Page - Analog Devices |
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LTC4282 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 32 page ![]() LTC4238 29 Rev. 0 For more information www.analog.com Second, check the temperature rise in channel 1 after startup when TMR times out under different overload conditions. In this example, IPT015N10N5 can take 60A with 40V across it for 100µs. The temperature rise in 20µs is insignificant under overload conditions. If the worst- case temperature rise in channel 1 is too high, better SOA MOSFET(s) must be selected for it. Layout Considerations For high current applications, PCB layout plays a critical role in minimizing current congestion as well as partition- ing the current between two channels. In parallel mode, to achieve the even split of current flow between the two channels, the two high current paths should have very similar layouts for the RSENSE and MOSFET placements. To achieve accurate current sensing, Kelvin connec- tions are also required. The SENSE+ and SENSE– lines should be laid out as differential signal pair. Their trace lengths to LTC4238 pins should be as short as possible. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable tem- perature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530μΩ/. Small resistances add up quickly in high cur- rent applications. To improve noise immunity, place the resistive voltage dividers for the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put the INTVCC bypass capacitor as close as possible between the INTVCC and GND pins. A 0.1μF capacitor, CF, from the UV pin (and OV pin through resistor R2) to GND also helps reject supply noise. Figure 11 shows a layout that addresses these issues. Note that a surge suppressor, Z1, is placed between supply and ground using wide traces. It is advised to avoid placing the ground plane under the power MOSFETs. If the MOSFETs overheat, the insulation could fail between the input voltage at their drains and an underlying ground plane. This could create a catastrophic short across the supply. APPLICATIONS INFORMATION Figure 11. Recommended PCB Layout 4238 F11 Z1 R3 R2 CF R1 R8 SENSE RESISTOR RS ILOAD ILOAD GND VIN UV OV FB |
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