LTC4282 datasheet(16/32 Pages) AD

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LTC4238

Rev. 0

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internally from VDD to VDSFB. For 12V systems, VDSFB

should be simply connected to SOURCE. For input volt-

ages larger than 12V, add a resistance of 10kΩ/V between

the VDSFB and SOURCE pins. For example, for 48V sys-

tems, a 360k resistor is required to be added between

the two pins.

Note that the SOA timer is independent of the current limit

set via the ISET pin. The current limit may be adjusted with

the ISET pin without the need to modify the thermal RC

network. However, if the sense resistor value is changed,

a modified thermal RC network will be required. Using a

large current limit threshold, such as 20mV, achieves the

greatest accuracy and dynamic range from the SOA timer.

Refer to Typical Performance Characteristics for the SOA

TMR pull-up currents at different ΔVSENSE1 and different

VDD – VDSFB voltages.

The configuration of the thermal RC network for a particu-

lar MOSFET starts with the selection of a desired num-

ber of resistive and capacitive elements. Their values are

decided based on the thermal impedance plot provided

by the MOSFET manufacturer. Three resistors and three

capacitors are usually enough to fit the plot fairly well

from 10μs to 100ms (Figure 1), which covers the timing

range of typical operating and fault conditions. If better

fitting accuracy or wider fitting range is desired, more

elements may be used. After the thermal RC network is

configured, the thermal quantities are then converted to

electric quantities according to Equation 3.

RE = k •Rθ

CE =

Cθ

(3)

where RE and CE are electric resistance and capacitance,

respectively and Rθ and Cθ are thermal resistance and

capacitance, respectively. The conversion constant k is

given by Equation 4.

VDS,MAX •ID,MAX

ITIMER(UP),MAX

•

VTIMER(TH)

ΔTMAX

(4)

• VDS,MAX = The Maximum drain-to-source voltage that

results in VDSFB at 12V below VDD.

• ID,MAX = 20mV/RSENSE1.

• ITIMER(UP),MAX = The TMR pull-up current correspond-

ing to the maximum power dissipation.

PMAX = VDS,MAX • ID,MAX

• VTMR(TH) = TMR rising threshold (2.56V).

• ΔTMAX = The Maximum allowable temperature rise of

the MOSFET.

For example, if VDS,MAX = 58V, ID,MAX = 40A, ITMR(UP),MAX

= 400μA and ΔTMAX = 110°C (175°C TJMAX – 65°C TA),

k = 1.4 • 105 [V2/°C]. A thermal RC network consisting of

three resistors and capacitors that represent the thermal

behavior of PSMN3R7-100BSE is shown in Figure 1.

FET-Bad Fault and Auto-Retry

A damaged MOSFET may have leakage from gate to

drain or have degraded RDS(ON). Debris on the board

may also produce leakage or a short from the GATE pin

to the SOURCE pin, the MOSFET drain, or to ground. In

these conditions the LTC4238 may not be able to pull the

GATE pin high enough to fully enhance the MOSFET, or

the MOSFET may not reach the intended RDS(ON) when the

GATE pin is fully enhanced. This can put the MOSFET in a

condition where the power in the MOSFET is higher than

its continuous power handling capability, even though the

current is below the current limit.

The LTC4238 monitors the integrity of the MOSFETs in

two ways, and acts on both of them in the same manner.

First, the LTC4238 monitors the voltage between the VDD

and SOURCE pins. A comparator detects a high DRAIN-

to-SOURCE voltage (VDS) whenever VDD to SOURCE volt-

age is greater than 100mV. Second, the LTC4238 moni-

tors the GATE voltage. The GATE voltage may not fully

enhance with a damaged MOSFET. A gate low condition is

detected if Gate-to-Source voltage is lower than 8V, and

that channel is not in active current limit.

When either a high DRAIN-to-SOURCE voltage or a gate

low condition is present for either or both MOSFETs while

they are commanded on, the FET-bad timer starts to run.

The logic determining FET-bad condition is in Figure 4.

The external timer capacitor on the TMRFET pin is charged

with a 20μA pull-up current. When the timer reaches the

2.56V rising threshold, a FET-bad fault condition is set, the

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