LTC4282 datasheet(22/32 Pages) AD

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LTC4238

Rev. 0

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APPLICATIONS INFORMATION

0.5m

PSMN3R7-100BSE

360k

93.1k

3.01k

4.22k

0.1µF

CFET

0.15µF

62k

5.23k

82nF

0.1µF

FLT#

TMR

VDD

CONFIG1

SENSE1–

SENSE1+

GATE1

SENSE2–

GATE2

SOURCE

VDSFB

LTC4238

SENSE2+

ISET

CONFIG2

INTVCC

TMRFET

GND

BACKPLANE PLUG-IN

BOARD

LOAD

VIN

48V

COMM

4238 F07

VOUT

16A

RBOTTOM

14.7k

RTOP

88.7k

Figure 7. 48V, 16A A Single MOSFET Implementation with HSSS Mode

low SOA MOSFETs (M1A and M1B) with a high current

limit to deliver the full load current. The turn-on sequence

is the opposite of that in the high stress staged start mode

as illustrated in Figure 5b: M2 turns on first and deliv-

ers a low inrush current due to the large sense resistor

RS2. Once the load is fully charged (FB pin is higher than

2.56V) and the start-up MOSFET is fully enhanced (VGATE2

> 8V) and not in active current limit, GATE1 turns on.

When the MOSFETs of both channels are fully enhanced,

the drain-to-source voltage is lower than 2V and FB pin

voltage is higher than 2.56V, power-good is asserted.

The current sense pins for both current limit circuits on

GATE1 and GATE2 must be connected to their corre-

sponding sense resistors. If an overcurrent event occurs,

both GATE1 and GATE2 stay in current limit to share the

stress. GATE1 turns off if the FB pin drops below 2.48V

or GATE2 turns off due to a fault, which is different from

the high stress staged start mode where GATE2 turns off

if GATE1 is in current limit.

The condition to start the FET-bad fault timer in this mode

is the same as in the parallel mode (see Table 2). Since

the FET-bad fault timer is running during the trickle start-

up while the load is slowly charged, the timer duration

must be programmed long enough to avoid turning off

M2 too early.

If the current limit timer is chosen, the TMR capacitor

will be charged only when channel 1 is in current limit.

A single, small TMR capacitor as shown in Figure 6a can

be used to configure a brief delay, which should be within

the worst SOA of M1A/M1B and M2. If the SOA timer is

chosen, an RC network that represents the electric model

for the thermal behavior of M1A or M1B should be con-

nected to TMR. Note that during startup when M1A and

M1B are turned off, the TMR pull-up current still relates

to the power dissipation in M1A and M1B, which is zero.

M2 should be selected so that its SOA allows it to be in

current limit longer than M1A or M1B. In this way M2 is

automatically protected when M1A and M1B turn off in

an overcurrent condition.

Single Driver Mode

Figure 7 shows a single MOSFET application. Configured

in high stress staged start mode, this implementation

behaves as other single Hot Swap controllers like the

LT4256 when the bypass MOSFETs are not stuffed and

the GATE2 pin is open.

LTC4282 Datasheet(PDF) 22 Page - Analog Devices

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