LTC4282 datasheet(27/32 Pages) AD

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LTC4238

Rev. 0

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capacitor, CF, is placed on the UV pin to prevent supply

glitches from turning off the GATE via UV or OV.

The FB divider is solved by picking R8 and solving for R7,

choosing 5.23k for R8.

VPWRGD(UP)

FBTH(RISING)

•R8 – R8

(16)

resulting in R7 = 62k.

Since the fast-current limit comparator is engaged at

120A, the input TVS needs to be capable of clamping a

120A surge at a voltage above the OV threshold but below

the 100V absolute maximum rating of the LTC4238 for

about 1μs. The SMC5K60A clamps 51.7A at 96.8V for

1ms and can dissipate 23kW for 10μs. Three of them are

required to sink 120A current.

In addition, a 0.1µF ceramic bypass capacitor is placed

on the INTVCC pin. No bypass capacitor is required on

the VDD pin.

Example 2: Low Stress Staged Start Mode with Basic

Timer

The second example has a line regulated 48V supply with

the voltage variation of ±10%. The output is a 2.5kW con-

stant power load. VUV(ON) = 36V and VOV(OFF) = 60V as

shown in Figure 6. The load capacitance is specified as CL

= 2500μF. The low stress staged start mode is chosen for

this example since the power exceeds 1500W and there

is no concern of large input steps. In LSSS, the FET bad

timer will run if GATE1 is low and not in ACL (Table 2),

which could happen when the power good voltage hasn’t

been reached. Therefore, the power good voltage is rec-

ommended to be lower than the input UV voltage. In this

example, VPWRGD(UP) is set to 33V. The current in chan-

nel 2 is usually only a small fraction of the maximum load

current, such as 10% or less. For this reason, its cur-

rent contribution during normal operation can be ignored

for the first phase of the design. Later channel 2 can be

accounted for or sized to make up for any shortfall in the

high current (channel 1) path, so that full power (2500W)

can be supplied at minimum input voltage (43V).

The maximum load current is calculated by Equation 17.

IL(MAX) = PL(MAX)/VS(MIN) = 2500W/43V ≈ 58A (17)

With the two channels decoupled (channel 2 dedicated to

start-up and channel 1 dedicated to passing the load cur-

rent), the overall design flow and design considerations in

some individual steps of the low stress staged start mode

are different from the parallel mode.

Step 1. Select sufficient bypass MOSFETs to carry the

maximum load current. For the maximum channel current

of 58A, two IPT015N10N5 (RDS(ON) < 1.5mΩ) devices

result in 1.26W per package, an acceptable dissipation

with airflow.

With full load, the worst-case voltage across the MOSFET

is about 58A • (1.5/2)mΩ = 43.5mV. The threshold for

starting the FET-bad timer is 100mV. There is sufficient

margin to account for inaccuracies before enabling the

TMRFET pull-up current. See detailed design consider-

ations in Example 1, Step 2.

Step 2. Configure the current limit and select the current

sense resistors. The current limit in this example should

cover the maximum load current, with enough margin to

account for device tolerances. Pick the minimum resis-

tance available for a single sense resistor, 200µΩ, which is

a metal element resistor. Select the current limit threshold

voltage by first assuming channel 1 carries the maximum

load current, then add a small current carried by the start-

up channel for the margin.

ΔVSENSE(MIN) = RS1 • IL(MAX) = 200µΩ • 58A ≈ 12mV

(18)

The resistor power dissipation of channel 1 is given by

Equation 21.

PS1 = ΔVSENSE(MIN) • IL(MAX) = 12mV • 58A = 696mW (19)

Which is well within the power limit of several Watts for

a metal element sense resistor.

As a last step, a 4mΩ sense resistor is chosen for a chan-

nel 2 current:

ILIM1=

∆VSENSE

RS2

12mV

4mΩ

= 3A

(20)

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