LTC4282 datasheet(28/32 Pages) AD

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LTC4238

Rev. 0

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so that the total current limit is calculated by Equation 21.

ILIM =ILIM1+ILIM2 =

12mV

200µΩ

+3A = 63A

(21)

Taking all tolerances into account, this provides sufficient

margin for the maximum load current of 58A.

Step 3. Design the TMR behavior. Since there is no con-

cern about a large input step, a short timer delay is chosen

for overcurrent turn-off. In the low stress staged start

mode the TMR function is a filtered circuit breaker and

a single timer capacitor on TMR works for this purpose.

Channel 1 dictates the timer capacitor selection since it

carries most of the load current. All of the channel 1 cur-

rent could be concentrated into a single MOSFET. The

current limit of channel 1 is 60A in this example, and

the MOSFET (IPT015N10N5) can handle 50V and 60A

for 80μs. It has been found that 20μs of circuit breaker

filtering is sufficient to reject noise encountered in most

systems, so the chosen MOSFET is up to the task. The

TMR pull-up current is 20μA, with a voltage threshold of

2.56V. Compute the timer capacitance for 20μs filter delay

using Equation 22.

CTMR =

ITMR(UP),MAX • tFILTER

VTMR(TH)

20µA • 20µs

2.56V

= 156pF

(22)

Select the next-larger available capacitance: CTMR =

180pF.

Step 4. Design the start-up channel (channel 2) and FET-

bad timer. At start-up in low stress staged start mode,

channel 2 charges the load capacitance with a small trickle

current. The necessary start-up time for a 2500μF load

capacitor is:

tCHAREGUP =

CL • V

PDISS,START-UP

• 2500µF •(53V)2

3A • 30% • 53V

= 74ms

(23)

APPLICATIONS INFORMATION

The FET bad timer must be set longer than the startup

time for the load capacitor to be fully charged. Meanwhile,

FET-bad timer should be short enough that the FET picked

for channel 2 can handle the start-up current with the full

drain to source voltage for this duration. With a 2× safety

margin, we choose:

CFET =

2 • tSTART-UP •ITMRFET(UP)

2.56V

2 • 74ms • 20µA

2.56V

= 1.2µF

(24)

The next larger available capacitance, 1.5µF, is used.

Since the start-up current is relatively low, a small, low

cost device may be used. PSMN7R6-100B, which can

stand the 30% foldback of 3A at 48V as a DC condition is

selected for this trickle channel. Its RDS(ON) is no higher

than 7.6mΩ. After startup, the worst-case power dissipa-

tion in this channel is (3A)2 • 7.6mΩ = 68mW, well within

the MOSFET capability.

Step 5. Run simulations to verify temperature rises in

both the channel 1 and channel 2 MOSFETs under all oper-

ating and fault conditions. This is a necessary step when

using a single capacitor current limit timer as selected

in Step 3.

First, check the temperature rise in the channel 2 MOSFET

(M2) during startup. The conditions include normal startup

into current limit to fully charge the 2500μF load capacitor

at the maximum input voltage. If the temperature rise is

too high in normal startup condition, a larger MOSFET

can be selected for channel 2. For the fault condition, the

worst-case power dissipated in MOSFET is same as the

max voltage (53V) across the MOSFET with 30% of full

current limit since the constant power profile is selected

for foldback. If the temperature rise is too high, the startup

current limit may be reduced by selecting a larger sense

resistor RS2. Using the conditions of this example, it is

found the worst-case temperature rise in M2 either in

normal startup condition or with fault resistors is lower

than 50°C. This verifies the selected channel 2 MOSFET,

PSMN7R6-100B, has more than enough SOA to handle

the worst-case dissipation.

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