LTC4282 datasheet(17/32 Pages) AD

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LTC4238

Rev. 0

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part turns off, and the GATE pins are pulled low with 10mA

to SOURCE and 1mA to ground. If the DRAIN-to-SOURCE

voltage falls below 100mV and the GATE low conditions

are cleared before the TMRFET reaches 2.56V threshold,

the TMRFET pin will discharge with 500μA. For a given

FET-bad time delay, tFET-BAD, use Equation 5 for setting

the timing capacitor’s value:

CTMRFET = tFET-BAD • 8[nF/ms]

(5)

Note that during start-up, the VDS high condition is present

because the voltage from drain-to-source is greater than

100mV. To avoid undesired turn-off, the FET-bad timer

duration must be long enough for the largest allowable

load to start up. FET-bad faults are disabled by grounding

the TMRFET pin.

The LTC4238 treats a FET-bad fault similar to an overcur-

rent fault. If a FET-bad fault is detected, the MOSFETs are

turned off and the TMRFET pin begins discharging with a

500μA pull-down current. When the TMRFET pin reaches

its 0.2V threshold, it will cycle up with 20μA and down

with 500μA 64 times to allow the MOSFET time to cool

down. When automatically retrying with FLT# pin tied to

UV pin, the resulting FET-bad duty cycle is 1.6%. After

the final time the TMRFET pin falls below its 0.2V low

threshold the MOSFETs are allowed to turn on again.

Undervoltage and Overvoltage Faults

The UV pin can be used to monitor a supply undervoltage

condition using an external resistive voltage divider. An

undervoltage fault occurs when the UV voltage falls below

its 2.2V falling threshold. An overvoltage fault occurs

when the OV voltage goes above its rising threshold of

2.56V. When either an undervoltage or overvoltage fault

occurs, the LTC4238 shuts off the GATE pins with a 10mA

current to SOURCE and a 1mA current to ground.

If the UV voltage subsequently rises back above the

threshold for 40ms, the GATEs can turn on again. If the

OV voltage subsequently falls back below the threshold,

the GATEs can turn on again immediately. The UV and OV

signals may be filtered by placing a capacitor, CF, between

the UV pin and GND.

Dual Gate Operation Modes

The LTC4238 features dual gate drivers that are config-

ured by the CONFIG1 and CONFIG2 pins into four dis-

tinct operation modes: single driver, parallel, high stress

staged start (HSSS), and low stress staged start (LSSS).

As shown in Table 2, each mode features specific SOA or

RDS(ON) benefits, GATE(s) on/off behavior, power good

signaling and fault detection logic.

All modes except LSSS support starting up with a resis-

tive load such as a heating element or incandescent lamp.

The modes of the dual gate drivers are selected together

with the foldback profile and TMR behavior by the status

of CONFIG1 and CONFIG2 pins as shown in Table 3.

Parallel

High current applications often demand several power

MOSFETs in parallel to reach a target RDS(ON) under 1mΩ

that is unavailable in a single MOSFET. In addition, divid-

ing the load current amongst multiple devices alleviates

the PCB current crowding problem with the use of a single

MOSFET.

Parallel MOSFETs share current well when their GATE-

to-SOURCE voltages are fully enhanced. However, when

the MOSFETs are limiting current, the mismatch between

gate thresholds will cause the MOSFET with the lowest

threshold to carry more current than the others. Since

threshold voltage has a negative temperature coefficient,

as this MOSFET heats it may carry even more current.

Eventually all the load current may be carried by a single

MOSFET. For this reason, when a group of MOSFETs are

operated in parallel only the SOA (Safe Operating Area)

of a single MOSFET is guaranteed.

The LTC4238 resolves this problem by offering two gate

drivers, each with an independent current limit circuit and

associated current sense pins. For configuration 4, 7, 8,

and 9 as shown in Table 3, these two gate drivers operate

APPLICATIONS INFORMATION

Figure 4. LOGIC Diagram for FET-Bad Timer

4238 F04

RUN

FET-BAD

TIMER

VCOMM > GATE ON THRESHOLD

VCC – SOURCE > 100mV

GATE1 < 8V

GATE1 NOT IN ACL

GATE2 < 8V

GATE2 ENABLED OR NOT IN ACL

(DEPENDING ON THE MODE)

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