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ADP2140 Datasheet(PDF) 4 Page - Analog Devices

Part # ADP2140
Description  3 MHz, 600 mA, Low Quiescent Current Buck with 300 mA LDO Regulator
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP2140 Datasheet(HTML) 4 Page - Analog Devices

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ADP2140
Data Sheet
Rev. B | Page 4 of 32
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Output Noise
OUTNOISE
VIN2 = VIN1 = 5 V, IOUT2 = 10 mA
10 Hz to 100 kHz, VOUT2 = 0.8 V
29
µV rms
10 Hz to 100 kHz, VOUT2 = 1.2 V
40
µV rms
10 Hz to 100 kHz, VOUT2 = 1.8 V
50
µV rms
10 Hz to 100 kHz, VOUT2 = 2.5 V
66
µV rms
10 Hz to 100 kHz, VOUT2 = 3.3 V
88
µV rms
Current Limit
ILIM
TJ = 25°C
360
500
760
mA
Input Leakage Current
ILEAK-LDO
EN2 = GND, VIN2 = 5.5 V and VOUT2 = 0 V
1
μA
Start-Up Time1
tSTART-UP
VOUT2 = 3.3 V, 300 mA load
70
µs
Soft Start Time2
SSTIME
VOUT2 = 3.3 V, 300 mA load
130
μs
ADDITIONAL FUNCTIONS
Undervoltage Lockout
UVLO
Input Voltage Rising
UVLORISE
2.23
2.3
V
Input Voltage Falling
UVLOFALL
2.05
2.16
V
EN Input
EN1, EN2 Input Logic High
VIH
2.3 V ≤ VIN1 ≤ 5.5 V
1.0
V
EN1, EN2 Input Logic Low
VIL
2.3 V ≤ VIN1 ≤ 5.5 V
0.27
V
EN1, EN2 Input Leakage
IEN-LKG
EN1, EN2 = VIN1 or GND
0.05
µA
EN1, EN2 = VIN1 or GND
1
µA
Shutdown Current
ISHUT
VIN1 = 5.5 V, EN1, EN2 = GND, TJ = −40°C to +85°C
0.3
1.2
μA
Thermal Shutdown
Threshold
TSSD
TJ rising
150
°C
Hysteresis
TSSD-HYS
20
°C
Power Good
Rising Threshold
PGRISE
92
%VOUT
Falling Threshold
PGFALL
86
%VOUT
Power-Good Hysteresis
PGHYS
6
%VOUT
Output Low
VOL
ISINK = 4 mA
0.2
V
Leakage Current
IOH
Power-good pin pull-up voltage = 5.5 V
1
μA
Buck to LDO Delay
tDELAY
PWM mode only
5
ms
Power-Good Delay
tRESET
PWM mode only
5
ms
1
Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 10% of the VOUTx nominal value.
2
Soft start time is defined as the time between VOUTx being at 10% to VOUTx being at 90% of the VOUTx nominal value.
3
Based on an endpoint calculation using 1 mA and 300 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1
TA = −40°C to +125°C
Buck
CMIN
7.5
10
µF
LDO
CMIN
0.7
1.0
µF
CAPACITOR ESR
TA = −40°C to +125°C
Ω
Buck
RESR
0.001
0.01
Ω
LDO
RESR
0.001
1
Ω
MINIMUM INDUCTOR
INDMIN
0.7
1
μH
1
The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.



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