ADP2140 datasheet(29/32 Pages) AD

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Data Sheet

ADP2140

Rev. B | Page 29 of 32

145

135

125

115

105

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

TOTAL POWER DISSIPATION (W)

500mm2

50mm2

0mm2

TJ MAX

Figure 93. Junction Temperature vs. Power Dissipation, TA = 65°C

135

125

115

105

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

TOTAL POWER DISSIPATION (W)

500mm2

50mm2

0mm2

TJ MAX

Figure 94. Junction Temperature vs. Power Dissipation, TA = 85°C

In cases where the board temperature is known, use the thermal

characterization parameter, ΨJB, to estimate the junction temper-

ature rise. Maximum junction temperature (TJ) is calculated

from the board temperature (TB) and power dissipation (PD)

using the formula

TJ = TB + (PD × ΨJB)

(5)

The typical ΨJB value for the 10-lead, 3 mm × 3 mm LFCSP is

16.9°C/W.

140

100

120

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

TOTAL POWER DISSIPATION (W)

TB = 25°C

TB = 50°C

TB = 65°C

TB = 85°C

TJ MAX

Figure 95. Junction Temperature vs. Power Dissipation

PCB LAYOUT CONSIDERATIONS

Improve heat dissipation from the package by increasing

the amount of copper attached to the pins of the ADP2140.

However, as listed in Table 10, a point of diminishing returns

is eventually reached, beyond which an increase in the copper

size does not yield significant heat dissipation benefits.

Poor layout can affect the ADP2140 buck performance causing

electromagnetic interference (EMI) and electromagnetic compa-

tibility (EMC) performance, ground bounce, and voltage losses;

thus, regulation and stability can be affected. Implement a good

layout using the following rules:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies and long, large tracks act like

antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Use a ground plane with several vias connected to the

component-side ground to reduce noise interference on

sensitive circuit nodes.

•

Use of 0402- or 0603-size capacitors achieves the smallest

possible footprint solution on boards where area is limited.

Figure 96. PCB Layout, Top

Figure 97. PCB Layout, Bottom

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