CP3UB26 datasheet(48/268 Pages) NSC

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10.3.1

Interrupt Vector Register (IVCT)

The IVCT register is a byte-wide read-only register which re-

ports the encoded value of the highest priority maskable in-

terrupt that is both asserted and enabled. The valid range is

from 10h to 3Fh. The register is read by the CPU during an

interrupt acknowledge bus cycle, and INTVECT is valid dur-

ing that time. It may contain invalid data while INTVECT is

updated.

INTVECT

The Interrupt Vector field indicates the highest

priority interrupt which is both asserted and

enabled.

10.3.2

Non-Maskable Interrupt Status Register

(NMISTAT)

The NMISTAT register is a byte-wide read-only register. It

holds the status of the current pending Non-Maskable Inter-

rupt (NMI) requests. On the CP3UB26, the external NMI in-

put is the only source of NMI interrupts. The NMISTAT

read.

EXT

The External NMI request bit indicates wheth-

er an external non-maskable interrupt request

has occurred. Refer to the description of the

EXNMI register below for additional details.

– No external NMI request.

– External NMI request has occurred.

10.3.3

External NMI Trap Control and Status Register

(EXNMI)

The EXNMI register is a byte-wide read/write register. It in-

dicates the current value of the NMI pin and controls the

NMI interrupt trap generation based on a falling edge of the

NMI pin. TST, EN and ENLCK are cleared on reset. When

writing to this register, all reserved bits must be written with

0 for the device to function properly

The EXNMI trap enable bit is one of two bits

that can be used to enable NMI interrupts.

The bit is cleared by hardware at reset and

whenever the NMI interrupt occurs (EXN-

MI.EXT set). It is intended for applications

where the NMI input toggles frequently but

nested NMI traps are not desired. For these

applications, the EN bit needs to be re-en-

abled before exiting the trap handler. When

used this way, the ENLCK bit should never be

set. The EN bit can be set and cleared by soft-

ware (software can set this bit only if EXN-

MI.EXT is cleared), and should only be set

after the interrupt base register and the inter-

rupt stack pointer have been set up.

– NMI interrupts not enabled by this bit (but

may be enabled by the ENLCK bit).

– NMI interrupts enabled.

The PIN bit indicates the state (non-inverted)

on the NMI input pin. This bit is read-only, data

written into it is ignored.

– NMI pin not asserted.

– NMI pin asserted.

ENLCK

The EXNMI trap enable lock bit is used to per-

manently enable NMI interrupts. Only a de-

vice reset can clear the ENLCK bit. This

allows the external NMI feature to be enabled

after the interrupt base register and the inter-

rupt stack pointer have been set up. When the

ENLCK bit is set, the EN bit is ignored.

– NMI interrupts not enabled by this bit (but

may be enabled by the EN bit).

– NMI interrupts enabled.

INTVECT

Reserved

EXT

Reserved

ENLCK

CP3UB26 Datasheet(PDF) 48 Page - National Semiconductor (TI)

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