CP3UB26 datasheet(88/268 Pages) NSC

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17.3.3

Main Event Register (MAEV)

The Main Event Register summarizes and reports the main

events of the USB transactions. This register provides read-

only access. The MAEV register is clear after reset.

WARN

The Warning Event bit indicates whether one

of the unmasked bits in the FIFO Warning

Event (FWEV) register has been set. This bit

is cleared by reading the FWEV register.

0 – No warning event occurred.

1 – A warning event has occurred.

ALT

The Alternate Event bit indicates whether one

of the unmasked ALTEV register bits has

been set. This bit is cleared by reading the AL-

TEV register.

0 – No alternate event has occurred.

1 – An alternate event has occurred.

TX_EV

The Transmit Event bit indicates whether any

of the unmasked bits in the Transmit Event

(TXEV) register (TXFIFOn or TXUNDRNn) is

set. Therefore, it indicates that an IN transac-

tion has been completed. This bit is cleared

when all the TX_DONE bits and the TXUN-

DRN bits in each Transmit Status (TXSn) reg-

ister are cleared.

0 – No transmit event has occurred.

1 – A transmit event has occurred.

FRAME

The Frame Event bit indicates whether the

frame counter has been updated with a new

value, due to receipt of a valid SOF packet on

the USB or to an artificial update if the frame

counter was unlocked or a frame was missed.

This bit is cleared when the register is read.

0 – The frame counter has not been updated.

1 – Frame counter has been updated.

NAK

The Negative Acknowledge Event indicates

whether one of the unmasked NAK Event

(NAKEV) register bits has been set. This bit is

cleared when the NAKEV register is read.

0 – No unmasked NAK event has occurred.

1 – An unmasked NAK event has occurred.

The Unlocked/Locked Detected bit is set

when the frame timer has either entered un-

locked condition from a locked condition, or

has re-entered a locked condition from an un-

locked condition as determined by the UL bit

in the Frame Number (FNH or FNL) register.

This bit is cleared when the register is read.

0 – Frame timer has not entered an unlocked

condition from a locked condition or re-

entered a locked condition from an un-

locked condition.

1 – Frame timer has either entered an un-

locked condition from a locked condition

or re-entered a locked condition from an

unlocked condition.

RX_EV

The Receive Event bit is set if any of the un-

masked bits in the Receive Event (RXEV) reg-

ister is set. It indicates that a SETUP or OUT

transaction has been completed. This bit is

cleared when all of the RX_LAST bits in each

Receive Status (RXSn) register and all RX-

OVRRN bits in the RXEV register are cleared.

0 – No receive event has occurred.

1 – A receive event has occurred.

INTR

The Master Interrupt Enable bit is hardwired

to 0 in the Main Event (MAEV) register; bit 7

in the Main Mask (MAMSK) register is the

Master Interrupt Enable.

0 – USB interrupts disabled.

1 – USB interrupts enabled.

17.3.4

Main Mask Register (MAMSK)

The MAMSK register masks out events reported in the

MAEV registers. A set bit enables the interrupts for the re-

spective event in the MAEV register. If the corresponding bit

is clear, interrupt generation for this event is disabled. This

clear after reset.

17.3.5

Alternate Event Register (ALTEV)

The ALTEV register summarizes and reports the further

events in the USB node. This register provides read-only ac-

cess. The ALTEV register is clear after reset.

DMA

The DMA Event bit indicates that one of the

unmasked bits in the DMA Event (DMAEV)

only and clear, when the DMAEV register is

cleared.

0 – No DMA event has occurred.

1 – A DMA event has occurred.

EOP

The End of Packet bit indicates whether a val-

id EOP sequence has been detected on the

USB. It is used when this device has initiated a

Remote wake-up sequence to indicate that the

Resume sequence has been acknowledged

and completed by the host. This bit is cleared

when the register is read.

0 – No EOP sequence detected.

1 – EOP sequence detected.

INTR RX_EV ULD NAK FRAME TX_EV ALT WARN

RESUME RESET SD5

SD3 EOP DMA Reserved

CP3UB26 Datasheet(PDF) 88 Page - National Semiconductor (TI)

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