CP3UB26 datasheet(96/268 Pages) NSC

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FLUSH

Writing a 1 to the Flush FIFO bit flushes all

data from the control endpoint FIFOs, resets

the endpoint to Idle state, clears the FIFO

read and write pointer, and then clears itself.

If the endpoint is currently using the FIFO0 to

transfer data on USB, flushing is delayed until

after the transfer is complete. The FLUSH bit

is cleared on reset. It is equivalent to the

FLUSH bit in the RXC0 register.

0 – Writing 0 has no effect.

1 – Writing 1 flushed the FIFOs.

IGN_IN

When the Ignore IN Tokens bit is set, the end-

point will ignore any IN tokens directed to its

configured address.

0 – Do not ignore IN tokens.

1 – Ignore IN tokens.

17.3.27 Transmit Data 0 Register (TXD0)

Data written to the TXD0 register is copied into the FIFO of

Endpoint 0 at the current location of the transmit write point-

er. The register allows write-only access from the CPU bus.

TXFD

The Transmit FIFO Data Byte is used to load

the transmit FIFO. Software is expected to

write only the packet payload data. The PID

and CRC16 are created automatically.

17.3.28 Receive Status 0 Register (RXS0)

The RXS0 register indicates status conditions for the bidi-

rectional Control Endpoint 0. To receive a SETUP packet af-

ter receiving a zero length OUT/SETUP packet, there are

two copies of this register in hardware. One holds the re-

ceive status of a zero length packet, and another holds the

status of the next SETUP packet with data. If a zero length

packet is followed by a SETUP packet, the first read of this

RX_LAST set and RCOUNT clear), and the second read in-

dicates the status of the SETUP packet. This register pro-

vides read-only access from the CPU bus. After reset it is

clear.

RCOUNT

The Receive Count field reports the number of

bytes presently in the RX FIFO. This number

is never larger than 8 for Endpoint 0.

RX_LAST

The Receive Last Bytes bit indicates that an

ACK was sent on completion of a successful

receive operation. This bit is unchanged for

zero-length packets. It is cleared when this

0 – No ACK was sent.

1 – An ACK was sent.

TOGGLE

The Toggle bit reports the PID used when re-

ceiving the packet. When clear, this bit indi-

cates that the last successfully received

packet had a DATA0 PID. When set, this bit in-

dicates that the packet had a DATA1 PID. This

bit is unchanged for zero-length packets. It is

cleared when this register is read.

0 – DATA0 PID was used.

1 – DATA1 PID was used.

SETUP

The Setup bit indicates that the setup packet

has been received. This bit is unchanged for

zero-length packets. It is cleared when this

0 – Setup packet has not been received.

1 – Setup packet has been received.

17.3.29 Receive Command 0 Register (RXC0)

The RXC0 register controls the mandatory Endpoint 0 when

used in receive direction. This register provides read/write

access from the CPU bus. It is clear after reset.

RX_EN

The Receive Enable bit enables receiving

packets. OUT packet reception is disabled af-

ter every data packet is received, or when a

STALL handshake is returned in response to

an OUT token. The RX_EN bit must be set to

re-enable data reception. Reception of SET-

UP packets is always enabled. In the case of

back-to-back SETUP packets (for a given

endpoint) where a valid SETUP packet is re-

ceived with no other intervening non-SETUP

tokens, the Endpoint Controller discards the

new SETUP packet and returns an ACK hand-

shake. If any other reasons prevent the End-

point Controller from accepting the SETUP

packet, it must not generate a handshake.

This allows recovery from a condition where

the ACK of the first SETUP token was lost by

the host.

0 – Receive disabled.

1 – Receive enabled.

IGN_OUT

The Ignore OUT Tokens bit controls whether

OUT tokens are ignored. When this bit is set,

the endpoint ignores any OUT tokens directed

to its configured address.

0 – Do not ignore OUT tokens.

1 – Ignore OUT tokens.

IGN_SETUP The Ignore SETUP Tokens bit controls wheth-

er SETUP tokens are ignored. When this bit is

set, the endpoint ignores any SETUP tokens

directed to its configured address.

0 – Do not ignore SETUP tokens.

1 – Ignore SETUP tokens.

TXFD

Res. SETUP TOGGLE RX_LAST

RCOUNT

Reserved

FLUSH IGN_SETUP IGN_OUT RX_EN

CP3UB26 Datasheet(PDF) 96 Page - National Semiconductor (TI)

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