CP3UB26 datasheet(6/268 Pages) NSC

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3.14

MICROWIRE/SPI

The Microwire/SPI (MWSPI) interface module supports syn-

chronous serial communications with other devices that

conform to Microwire or Serial Peripheral Interface (SPI)

specifications. It supports 8-bit and 16-bit data transfers.

The Microwire interface allows several devices to communi-

cate over a single system consisting of four wires: serial in,

serial out, shift clock, and slave enable. At any given time,

the Microwire interface operates as the master or a slave.

The Microwire interface supports the full set of slave select

for multi-slave implementation.

In master mode, the shift clock is generated on-chip under

software control. In slave mode, a wake-up out of a low-

power mode may be triggered using the Multi-Input Wake-

Up module.

3.15

ACCESS.BUS INTERFACE

The ACCESS.bus interface module (ACB) is a two-wire se-

rial interface compatible with the ACCESS.bus physical lay-

er. It is also compatible with Intel’s System Management

Bus (SMBus) and Philips’ I2C bus. The ACB module can be

configured as a bus master or slave, and it can maintain bi-

directional communications with both multiple master and

slave devices.

The ACCESS.bus receiver can trigger a wake-up condition

out of the low-power modes through the Multi-Input Wake-

Up module.

3.16

MULTI-FUNCTION TIMER

The Multi-Function Timer (MFT) module contains a pair of

16-bit timer/counter registers. Each timer/counter unit can

be configured to operate in any of the following modes:

— Processor-Independent

Pulse

Width

Modulation

(PWM) mode: Generates pulses of a specified width

and duty cycle and provides a general-purpose timer/

counter.

— Dual Input Capture mode: Measures the elapsed time

between occurrences of external event and provides

a general-purpose timer/counter.

— Dual Independent Timer mode: Generates system

timing signals or counts occurrences of external

events.

— Single Input Capture and Single Timer mode: Pro-

vides one external event counter and one system tim-

er.

3.17

TIMING AND WATCHDOG MODULE

The Timing and Watchdog Module (TWM) contains a Real-

Time timer and a Watchdog unit. The Real-Time Clock Tim-

ing function can be used to generate periodic real-time

based system interrupts. The timer output is one of 16 in-

puts to the Multi-Input Wake-Up module which can be used

to exit from a power-saving mode. The Watchdog unit is de-

signed to detect the application program getting stuck in an

infinite loop resulting in loss of program control or “runaway”

programs. When the watchdog triggers, it resets the device.

The TWM is clocked by the low-speed System Clock.

3.18

VERSATILE TIMER UNIT

The Versatile Timer Unit (VTU) module contains four inde-

pendent timer subsystems, each operating in either dual 8-

bit PWM configuration, as a single 16-bit PWM timer, or a

16-bit counter with two input capture channels. Each of the

four timer subsystems offer an 8-bit clock prescaler to ac-

commodate a wide range of frequencies.

3.19

TRIPLE CLOCK AND RESET

The Triple Clock and Reset module generates a high-speed

main System Clock from an external crystal network. It also

provides the main system reset signal and a power-on reset

function.

This module generates a slow System Clock (32.768 kHz)

from an optional external crystal network. The Slow Clock is

used for operating the device in a low-power mode. The

32.768 kHz external crystal network is optional, because

the low speed System Clock can be derived from the high-

speed clock by a prescaler. Also, two independent clocks di-

vided down from the high speed clock are available on out-

put pins.

The Triple Clock and Reset module provides the clock sig-

nals required for the operation of the various CP3UB26 on-

chip modules. From external crystal networks, it generates

the Main Clock, which can be scaled up to 24 MHz from an

external 12 MHz input clock, and a 32.768 kHz secondary

System Clock. The 12 MHz external clock is primarily used

as the reference frequency for the on-chip PLL. The clock

for modules which require a fixed clock rate (e.g. the CVSD/

PCM transcoder) is also generated through prescalers from

the 12 MHz clock. The PLL may be used to drive the high-

speed System Clock through a prescaler. Alternatively, the

high speed System Clock can be derived directly from the

12 MHz Main Clock.

In addition, this module generates the device reset by using

reset input signals coming from an external reset and vari-

ous on-chip modules.

3.20

POWER MANAGEMENT

The Power Management Module (PMM) improves the effi-

ciency of the device by changing the operating mode and

power consumption to match the required level of activity.

The device can operate in any of four power modes:

— Active: The device operates at full speed using the

high-frequency clock. All device functions are fully op-

erational.

— Power Save: The device operates at reduced speed

using the Slow Clock. The CPU and some modules

can continue to operate at this low speed.

— Idle: The device is inactive except for the Power Man-

agement Module and Timing and Watchdog Module,

which continue to operate using the Slow Clock.

— Halt: The device is inactive but still retains its internal

state (RAM and register contents).

CP3UB26 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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