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PC8374L Datasheet(PDF) 149 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 149 Page - National Semiconductor (TI) |
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149 / 239 page  8.0 Health Management (HM) (Continued) Revision 1.1 149 www.national.com 8.4.10 HM Interrupt Status Register 3 (HMINT_STS3) Event status register 3. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Power Well: VSB3 Location: Offset 09h Type: R/W1C 8.4.11 HM Interrupt Enable Register 3(HMINT_EN3) Interrupt enable register 3. Power Well: VDD3 Location: Offset 0Ah Type: R/W Bit 76543210 Name Reserved CRIT3_EV CRIT2_EV CRIT1_EV Reset 00000000 Bit Description 7-3 Reserved. 2 CRIT3_EV. Is set to 1 when a Temperature Zone3 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared 1 CRIT2_EV. Is set to 1 when a Temperature Zone2 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared 0 CRIT1_EV. Is set to 1 when a Temperature Zone1 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared Bit 76543210 Name Reserved CRIT3_EN CRIT2_EN CRIT1_EN Reset 0 0 0 0 0 0 0 0 Bit Description 7-3 Reserved. 2 CRIT3_EN. When set to 1, enables IRQ generation on setting of CRIT3_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ 1 CRIT2_EN. When set to 1, enables IRQ generation on setting of CRIT2_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ 0 CRIT1_EN. When set to 1, enables IRQ generation on setting of CRIT1_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ Winbond Electronics Corp. Advanced PC Product Center |
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