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MCT8316Z Datasheet(PDF) 48 Page - Texas Instruments |
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MCT8316Z Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 100 page  8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To overcome this problem, MCT8316Z-Q1 has built in internal PWM clock which is used to turn high-side FET back on once it is disabled after exceeding ILIMIT threshold. In SPI variant MCT8316Z-Q1, this internal PWM clock can be configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant MCT8316Z-Q1 PWM internal clock is set to 20 kHz. Figure 8-38 shows operation with 100 % duty cycle. PWM ILIMIT OUTx Bridge Operating in Brake Mode Time Internal PWM Figure 8-38. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle MCT8316Z-Q1 SLVSGO3 – DECEMBER 2021 www.ti.com 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: MCT8316Z-Q1 |
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