MCT8316Z datasheet(68/100 Pages) TI

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8.6.2.2 Control_Register_2A Register (Offset = 4h) [Reset = 80h]

Control_Register_2A is shown in Control_Register_2A Register and described in Control_Register_2A Register

Field Descriptions.

Return to the CONTROL Registers.

Figure 8-53. Control_Register_2A Register

RESERVED

SDO_MODE

SLEW

PWM_MODE

CLR_FLT

R/W-2h

R/W-0h

W1C-0h

Table 8-19. Control_Register_2A Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

Reserved

SDO_MODE

R/W

SDO Mode Setting

0h = SDO IO in Open Drain Mode

1h = SDO IO in Push Pull Mode

4-3

SLEW

R/W

Slew Rate Settings

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 125 V/µs

3h = Slew rate is 200 V/µs

2-1

PWM_MODE

R/W

Device Mode Selection

0h = Asynchronous rectification with analog Hall

1h = Asynchronous rectification with digital Hall

2h = Synchronous rectification with analog Hall

3h = Synchronous rectification with digital Hall

CLR_FLT

W1C

Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after

being written.

MCT8316Z-Q1

SLVSGO3 – DECEMBER 2021

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