MCT8316Z datasheet(20/100 Pages) TI

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8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the driver.

Note

TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into

internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on

power up or the device will enter internal test mode.

Table 8-1. MCT8316Z-Q1 External Components

COMPONENTS

PIN 1

PIN 2

RECOMMENDED

CVM1

PGND

X5R or X7R, 0.1-µF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the device

CVM2

PGND

≥ 10-µF, TI recommends a capacitor voltage rating at

least twice the normal operating voltage of the device

CCP

X5R or X7R, 16-V, 1-µF capacitor

CFLY

CPH

CPL

X5R or X7R, 47-nF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the pin

CAVDD

AVDD

AGND

X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to

accurately regulate output voltage, capacitor should

have effective capacitance between 0.7-µF to 1.3-µF

at 3.3-V across operating temperature.

CBK

SW_BK

GND_BK

X5R or X7R, 22-µF, buck-output rated capacitor. TI

recommends a capacitor voltage rating at least twice

the normal operating voltage of the pin

LBK

SW_BK

FB_BK

Output inductor

RnFAULT

VCC

nFAULT

5.1-kΩ, Pullup resistor

RMODE

MODE

AGND or AVDD

MCT8316Z hardware interface

RSLEW

SLEW

AGND or AVDD

MCT8316Z hardware interface

RADVANCE

ADVANCE

AGND or AVDD

MCT8316Z hardware interface

RVSEL_BK

VSEL_BK

AGND or AVDD

MCT8316Z hardware interface

CILIM

ILIM

AGND

X5R or X7R, 0.1-µF, AVDD-rated capacitor (Optional)

8.3.1 Output Stage

The MCT8316Z-Q1 device consists of an integrated 95-mΩ (combined high-side and low-side FET's on-state

resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the

proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to

providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side

MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the

motor-supply voltage.

8.3.2 PWM Control Mode (1x PWM Mode)

The MCT8316Z-Q1 family of devices provides seven different control modes to support various commutation

and control methods. The MCT8316Z-Q1 device provides a 1x PWM control mode for driving the BLDC motor

in trapezoidal current-control mode. The MCT8316Z-Q1 device uses 6-step block commutation tables that are

stored internally. This feature lets a three-phase BLDC motor be controlled using a single PWM sourced from a

simple controller. The PWM is applied on the PWM pin and determines the output frequency and duty cycle of

the half-bridges.

The MCT8316Z-Q1 family of devices supports both analog and digital hall inputs by changing mode input

setting. Differential hall inputs should be connected to HPx and HNx pins (see Figure 8-3). Digital hall inputs

should be connected to the HPx pins while keeping the HNx pins floating (see Figure 8-4).

MCT8316Z-Q1

SLVSGO3 – DECEMBER 2021

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