AD9161BBCZ datasheet(45/144 Pages) AD

45 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 45 of 45

or ADDRINC_M is 1, the multicycle addresses are incremented.

When ADDRINC or ADDRINC_M is 0, the addresses are decre-

mented. A new write cycle can always be initiated by bringing

CS high and then low again.

To prevent confusion and to ensure consistency between devices,

the chip tests the first nibble following the address phase, ignoring

the second nibble. This test is completed independently from the

LSB first bits and ensures that there are extra clock cycles following

the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of

the first nibble only applies when writing to Register 0x000.

R/W A14 A13

A2 A1 A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

Figure 139. Serial Register Interface Timing, MSB First, Register 0x000, Bit 5

and Bit 2 = 0

A0 A1 A2

A12 A13 A14

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

R/W

Figure 140. Serial Register Interface Timing, LSB First, Register 0x000, Bit 5

and Bit 2 = 1

SCLK

SDIO

DATA BIT n – 1

DATA BIT n

tDV

Figure 141. Timing Diagram for Serial Port Register Read

SCLK

SDIO

INSTRUCTION BIT 14

INSTRUCTION BIT 0

INSTRUCTION BIT 15

tDS

tDH

tPWH

tPWL

Figure 142. Timing Diagram for Serial Port Register Write

AD9161BBCZ Datasheet(PDF) 45 Page - Analog Devices

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