AD9161BBCZ datasheet(51/144 Pages) AD

51 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 51 of 51

LANE 0 DESERIALIZED

AND DESCRAMBLED DATA

LANE 0 DATA CLOCK

SERDIN0±

FIFO

SERDIN7±

FIFO

CROSS-

BAR

SWITCH

LANE 7 DESERIALIZED

AND DESCRAMBLED DATA

LANE 7 DATA CLOCK

PCLK

DATA LINK LAYER

SPI CONTROL

SYSREF±

SYNCOUTx±

SYSTEM CLOCK

PHASE DETECT

LANE 0 OCTETS

LANE 7 OCTETS

QUAD-BYTE

DEFRAMER

QBD

Figure 150. Data Link Layer Block Diagram

L RECEIVE LANES

(LATEST ARRIVAL)

L ALIGNED

RECEIVE LANES

0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL

K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER

A = K28.3 LANE ALIGNMENT SYMBOL

F = K28.7 FRAME ALIGNMENT SYMBOL

R = K28.0 START OF MULTIFRAME

Q = K28.4 START OF LINK CONFIGURATION DATA

C = JESD204x LINK CONFIGURATION PARAMETERS

D = Dx.y DATA SYMBOL

4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL

L RECEIVE LANES

(EARLIEST ARRIVAL)

KK KKKK KRDD

KK KRDD

DD AR Q C

D DARD D

DDAR DD

KK KKKK KRDD

DD AR Q C

DDAR DD

Figure 151. Lane Alignment During ILAS

JESD204B Serial Link Establishment

A brief summary of the high speed serial link establishment

process for Subclass 1 is provided. See Section 5.3.3 of the

JESD204B specifications document for complete details.

Step 1: Code Group Synchronization

Each receiver must locate /K/ (K28.5) characters in its input

data stream. After four consecutive /K/ characters are detected

on all link lanes, the receiver block deasserts the SYNCOUT±

signal to the transmitter block at the receiver LMFC edge.

The transmitter captures the change in the SYNCOUT± signal

and at a future transmitter LMFC rising edge starts the ILAS.

Step 2: Initial Lane Alignment Sequence

The main purposes of this phase are to align all the lanes of the

link and to verify the parameters of the link.

Before the link is established, write each of the link parameters

to the receiver device to designate how data is sent to the

receiver block.

The ILAS consists of four or more multiframes. The last character

of each multiframe is a multiframe alignment character, /A/.

The first, third, and fourth multiframes are populated with

predetermined data values. Note that Section 8.2 of the JESD204B

specifications document describes the data ramp that is expected

during ILAS. The AD9161/AD9162 do not require this ramp.

The deframer uses the final /A/ of each lane to align the ends of

the multiframes within the receiver. The second multiframe

contains an /R/ (K.28.0), /Q/ (K.28.4), and then data

corresponding to the link parameters. Additional multiframes

can be added to the ILAS if needed by the receiver. By default,

the AD9161/AD9162 use four multiframes in the ILAS (this can

be changed in Register 0x478). If using Subclass 1, exactly four

multiframes must be used.

After the last /A/ character of the last ILAS, multiframe data

begins streaming. The receiver adjusts the position of the /A/

character such that it aligns with the internal LMFC of the

receiver at this point.

AD9161BBCZ Datasheet(PDF) 51 Page - Analog Devices

AD9161BBCZ Datasheet(HTML) 51 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL