AD9161BBCZ datasheet(64/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 64 of 144

Table 33. Sync Assertion Mask (SYNC_ASSERT_MASK)

Addr.

Bit No.

Bit Name

Description

0x47D

BDE

Set to 1 to assert SYNCOUT± if

the disparity error count

reaches the threshold

NIT

Set to 1 to assert SYNCOUT± if

the NIT error count reaches

the threshold

UEK

Set to 1 to assert SYNCOUT± if

the UEK character error

count reaches the threshold

CGS, Frame Sync, Checksum, and ILAS Monitoring

that each stage of the JESD204B link establishment has

occurred.

Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link

Lane x received at least four K28.5 characters and passed code

group synchronization.

Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x

completed initial frame synchronization.

Bit x of GOOD_CHECKSUM (Register 0x472) is high if the

checksum sent over the lane matches the sum of the JESD204B

parameters sent over the lane during ILAS for Link Lane x. The

parameters can be added either by summing the individual fields

in registers or summing the packed register. If Register 0x300,

Bit 6 = 0 (default), the calculated checksums are the lower eight

bits of the sum of the following fields: DID, BID, LID, SCR, L − 1,

F − 1, K − 1, M − 1, N − 1, SUBCLASSV, NP − 1, JESDV, S − 1,

and HD. If Register 0x300, Bit 6 = 1, the calculated checksums

are the lower eight bits of the sum of Register 0x400 to

Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link

Lane x passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x4B8,

Bits[3:0]. The IRQ event status can be read at Register 0x4BA,

Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA,

Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to

reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to

reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to

reset the ILAS IRQ.

See the Interrupt Request Operation section for more information.

Configuration Mismatch IRQ

The AD9161/AD9162 have a configuration mismatch flag that

is available as an IRQ event. Use Register 0x4B9, Bit 0 to enable

the mismatch flag (it is enabled by default), and then use

signal. See the Interrupt Request Operation section for more

information.

The configuration mismatch event flag is high when the link

configuration settings (in Register 0x450 to Register 0x45D) do

not match the JESD204B transmitted settings (Register 0x400 to

This function is different from the good checksum flags in

ted checksum matches a calculated checksum based on the

transmitted settings. The configuration mismatch event ensures

that the transmitted settings match the configured settings.

HARDWARE CONSIDERATIONS

See the Applications Information section for information on

hardware considerations.

AD9161BBCZ Datasheet(PDF) 64 Page - Analog Devices

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