AD9161BBCZ datasheet(95/144 Pages) AD

95 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 95 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

Bits[5:0]

Capacitance

CLK+

CLK−

000000

000001

000010

…

011111

100000

100001

100010

111111

0x080 CLK_PD

[7:1] RESERVED

Reserved.

0x0

DACCLK_PD

DAC clock power-down. Powers

down the DAC clock circuitry.

0x1

R/W

0 Power up.

1 Power down.

0x082 CLK_DUTY

CLK_DUTY_EN

Enable duty cycle control.

0x1

R/W

CLK_DUTY_OFFSET_EN

Enable duty cycle offset.

0x0

R/W

CLK_DUTY_BOOST_EN

Enable duty cycle range boost.

Extends range to ±5% at cost of

1 dB to 2 dB worse phase noise.

0x0

R/W

[4:0] CLK_DUTY_PRG

Program the duty cycle offset.

5-bit signed magnitude field,

with the MSB as the sign bit and

the four LSBs as the magnitude

from 0 to 15. A larger

magnitude skews duty cycle to

a greater amount. Range is

±3%.

0x0

R/W

0x083 CLK_CRS_CTRL

CLK_CRS_EN

Enable clock cross control

adjustment.

0x1

R/W

[6:4] RESERVED

Reserved.

0x0

[3:0] CLK_CRS_ADJ

Program the clock crossing

point.

0x0

R/W

0x084 PLL_REF_CLK_PD

[7:6] RESERVED

Reserved.

0x0

[5:4] PLL_REF_CLK_RATE

PLL reference clock rate

multiplier.

0x0

R/W

00 Normal rate (1×) PLL reference

clock.

01 Double rate (2×) PLL reference

clock.

10 Quadruple rate (4×) PLL

reference clock.

11 Disable the PLL reference clock.

[3:1] RESERVED

Reserved.

0x0

PLL_REF_CLK_PD

PLL reference clock power-

down.

0x0

R/W

0 Enable the PLL reference clock.

1 Power down the PLL reference

clock.

0x088 SYSREF_CTRL0

[7:4] RESERVED

Reserved.

0x0

HYS_ON

SYSREF± hysteresis enable. This

bit enables the programmable

hysteresis control for the

SYSREF± receiver.

0x0

R/W

SYSREF_RISE

Use SYSREF± rising edge.

0x0

R/W

AD9161BBCZ Datasheet(PDF) 95 Page - Analog Devices

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