AD9161BBCZ datasheet(71/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 71 of 144

There are several transmit enable features, including a TX_

ENABLE register that can be used to squelch data at several

points in the datapath or configure the TX_ENABLE pin to do

likewise.

Transmit Enable

The transmit enable feature can be configured either as a SPI

controlled function or a pin controlled function. It can be used

for several different purposes. The SPI controlled function has

less accurate timing due to its reliance on a microcontroller to

program it; therefore, it is typically used as a preventative measure

at power-up or when configuring the device.

The SPI controlled TX_ENABLE function can be used to zero

the input to the digital datapath or to zero the output from the

digital datapath, as shown in Figure 174. If the input to the

digital datapath is zeroed, any filtering that is selected filters the

0 signal, causing a gradual ramp-down of energy in the digital

datapath. If the digital datapath is bypassed, as in 1÷ mode, the

data at the input to the DAC immediately drops to zero.

The TX_ENABLE pin can be used for more accurate timing

when enabling or disabling the DAC output. The effect of the

TX_ENABLE pin can be configured by the same TX_ENABLE

tions, and it can be made to have the same effects as the SPI

controlled function, namely to zero the input to the digital

datapath or to zero the output from the digital datapath. In

addition, the TX_ENABLE pin can also be configured to ramp

down (or up) the full-scale current of the DAC. The ramp down

reduces the output power of the DAC by about 20 dB from full

scale to the minimum output current.

The TX_ENABLE pin can also be programmed to reset the

NCO phase accumulator. See Table 38 for a description of the

settings available for the TX_ENABLE function.

DATAPATH PRBS

The datapath PRBS can verify that the AD9161/AD9162 datapaths

receive and correctly decode data. The datapath PRBS verifies

that the JESD204B parameters of the transmitter and receiver

match, the lanes of the receiver are mapped appropriately, the lanes

are appropriately inverted, and, if necessary, the start-up routine

is correctly implemented.

To run the datapath PRBS test, complete the following steps:

1. Set up the device in the desired operating mode using the

start-up sequence.

2. Send PRBS7 or PRBS15 data.

3. Write Register 0x14, Bit 2 = 0 for PRBS7 or 1 for PRBS15.

4. Write Register 0x14B, Bits[1:0] = 0b11 to enable and reset

the PRBS test.

5. Write Register 0x14B, Bits[1:0] = 0b01 to enable the PRBS

test and release reset.

6. Wait 500 ms.

7. Check the status of the PRBS by checking the IRQ for the

I and Q path PRBS as described in the Datapath PRBS IRQ

section.

8. Read Register 0x14B, Bits [7:6]. Bit 6 is 0 if the I channel

has any errors. Bit 7 is 0 if the Q channel has any errors.

9. Read Register 0x14C to read the error count for the I channel.

10. Read Register 0x14D to read the error count for the Q

channel. The PRBS processes 32 bits at a time and

compares the 32 new bits to the previous set of 32 bits. It

detects and reports only one error in every group of 32 bits;

therefore, the error count partly depends on when the

errors are seen.

For example, see the following sequence:

•

Bits: 32 good, 31 good, 1 bad; 32 good [2 errors]

•

Bits: 32 good, 22 good, 10 bad; 32 good [2 errors]

•

Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good

[3 errors]

DATAPATH PRBS IRQ

The PRBS fail signals for the I and Q path are available as IRQ

events. Use Register 0x020, Bits [1:0] to enable the fail signals,

and then use Register 0x024, Bits [1:0] to read back the status

and reset the IRQ signals. See the Interrupt Request Operation

section for more information.

Table 38. TX_ENABLE Settings

Setting

Description

Bit 7

SPI control: zero data to the DAC

SPI control: allow data to pass to the DAC

Bit 6

SPI control: zero data at input to the datapath

SPI control: allow data to enter the datapath

Bits[5:4]

N/A1

Reserved

Bit 3

Use SPI writes to reset the NCO2

Use TX_ENABLE to reset the NCO

Bit 2

Use SPI control to zero data to the DAC

Use TX_ENABLE pin to zero data to the DAC

Bit 1

Use SPI control to zero data at the input to the datapath

Use TX_ENABLE pin to zero data at input to the datapath

Bit 0

Use SPI registers to control the full-scale current

Use TX_ENABLE pin to control the full-scale current

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