AD9161BBCZ datasheet(55/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 55 of 144

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

ALIGNED DATA

AT Rx OUTPUT

DATA AT

Tx INPUT

DATA

DSP

CHANNEL

LOGIC DEVICE

(JESD204B Tx)

JESD204B Rx

DAC

LINK DELAY = DELAYFIXED + DELAYVARIABLE

Figure 154. JESD204B Link Delay = Fixed Delay + Variable Delay

Link Delay

The link delay of a JESD204B system is the sum of the fixed and

variable delays from the transmitter, channel, and receiver as

shown in Figure 154.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B specifica-

tion states that the LMFC period must be larger than the maximum

link delay. For the AD9161/AD9162, this is not necessarily the

case; instead, the AD9161/AD9162 use a local LMFC for each

link (LMFCRx) that can be delayed from the SYSREF± aligned

LMFC. Because the LMFC is periodic, this delay can account

for any amount of fixed delay. As a result, the LMFC period

must only be larger than the variation in the link delays, and the

AD9161/AD9162 can achieve proper performance with a smaller

total latency. Figure 155 and Figure 156 show a case where the link

delay is greater than an LMFC period. Note that it can be

accommodated by delaying LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 155. Link Delay > LMFC Period Example

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC_DELAY

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 156. LMFC_DELAY_x to Compensate for Link Delay > LMFC

The method to select the LMFCDel (Register 0x304) and

LMFCVar (Register 0x306) variables is described in the Link

Delay Setup Example, With Known Delays section.

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then LMFCVar

is written into the receive buffer delay (RBD) to absorb all link

delay variation. This write ensures that all data samples have

arrived before reading. By setting these to fixed values across

runs and devices, deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from 1 frame clock cycle to K frame clock cycles, and the RBD

of the AD9161/AD9162 takes values from 0 PCLK cycle to

10 PCLK cycles. As a result, up to 10 PCLK cycles of total delay

variation can be absorbed. LMFCVar and LMFCDel are both in

PCLK cycles. The PCLK factor, or number of frame clock cycles

per PCLK cycle, is equal to 4/F. For more information on this

relationship, see the Clock Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

to Register 0x306 for all devices in the system.

Link Delay Setup Example, With Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 157 is demonstrated in the

following steps. Note that this example is in Subclass 1 to

achieve deterministic latency, which has a PCLK factor (4/F) of

2 frame clock cycles per PCLK cycle, and uses K = 32

(frames/multiframe). Because PCBFixed << PCLK Period, PCB

Fixed is negligible in this example and not included in the

calculations.

1. Find the receiver delays using Table 7.

RxFixed = 12 PCLK cycles

RxVar = 2 PCLK cycles

2. Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

gigabit transceiver on a Virtex-6 FPGA) states that the

delay is 56 ± 2 byte clock cycles.

AD9161BBCZ Datasheet(PDF) 55 Page - Analog Devices

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