AD9161BBCZ datasheet(5/144 Pages) AD

5 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 5 of 144

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DVDD_1P2

1.14

1.2

1.326

PLL_LDO_VDD12

1.14

1.2

1.326

PLL_CLK_VDD12

Can connect to PLL_LDO_VDD12

1.14

1.2

1.326

SYNC_VDD_3P3

3.135

3.3

3.465

BIAS_VDD_1P2

Can connect to VDD_1P2

1.14

1.2

1.326

VDDx is VDD12_CLK, DVDD, VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any clock speed over 5.1 GSPS requires a maximum junction temperature of 105°C to avoid

damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.

See Table 2 for the complete details on the guaranteed speed performance.

FIR85 is the finite impulse response filter with 85 dB digital attenuation that implements 2× NRZ mode.

The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9162, the minimum interpolation factor is 1.

Therefore, with fDAC = 6 GSPS, fDAC adjusted = 6 GSPS. For the AD9161, the minimum interpolation is 2×. Therefore, with fDAC = 6 GSPS, fDAC adjusted = 3 GSPS. When

FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation increases to 2× (interpolation

value). Thus, for the AD9162, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 2×, and the adjusted DAC update rate = 6 GSPS.

See the Clock Input section for more details.

For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.

IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.

DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,

VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of

105°C to avoid damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.

Table 2.

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

MAXIMUM DAC UPDATE RATE

VDDx = 1.2 V ± 5%

TJMAX = 25°C

6.0

GSPS

TJMAX = 85°C

5.6

GSPS

TJMAX = 105°C

5.4

GSPS

VDDx = 1.2 V ± 2%

TJMAX = 25°C

6.1

GSPS

TJMAX = 85°C

5.8

GSPS

TJMAX = 105°C

5.6

GSPS

VDDx = 1.3 V ± 2%

TJMAX = 25°C

6.4

GSPS

TJMAX = 85°C

6.2

GSPS

TJMAX = 105°C

6.0

GSPS

TJMAX is the maximum junction temperature.

POWER SUPPLY DC SPECIFICATIONS

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

8 LANES, 2× INTERPOLATION (80%), 3 GSPS

Numerically controlled oscillator (NCO) on,

FIR85 on

Analog Supply Currents

VDD25_DAC = 2.5 V

93.8

100

VDD12A = 1.2 V

3.7

150

µA

VDD12_CLK = 1.2 V

229

279

VNEG_N1P2 = −1.2 V

−119

−112

Digital Supply Currents

DVDD = 1.2 V

Includes VDD12_DCD/DLL

621.3

971

IOVDD1 = 2.5 V

2.5

2.7

AD9161BBCZ Datasheet(PDF) 5 Page - Analog Devices

AD9161BBCZ Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL