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AD9161BBCZ Datasheet(PDF) 117 Page - Analog Devices

Part # AD9161BBCZ
Description  11-Bit/16-Bit, 12 GSPS, RF Digital-to-Analog Converters
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9161BBCZ Datasheet(HTML) 117 Page - Analog Devices

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Data Sheet
AD9161/AD9162
Rev. D | Page 117 of 144
Hex.
Addr. Name
Bits Bit Name
Settings
Description
Reset
Access
0x41E COMPSUM2_REG
[7:0] LL_FCMP2
Computed checksum on Lane 2.
Computed checksum for Lane 2
(see description for Register
0x40E).
0x0
R
0x422 LID3_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID3
Received ILAS LID configuration
on Lane 3. Lane identification
for Lane 3.
0x0
R
0x425 CHECKSUM3_REG
[7:0] LL_FCHK3
Received checksum during ILAS
on Lane 3. Checksum for Lane 3.
0x0
R
0x426 COMPSUM3_REG
[7:0] LL_FCMP3
Computed checksum on Lane 3.
Computed checksum for Lane 3
(see description for
Register 0x40E).
0x0
R
0x42A LID4_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID4
Received ILAS LID configuration
on Lane 4. Lane identification
for Lane 4.
0x0
R
0x42D CHECKSUM4_REG
[7:0] LL_FCHK4
Received checksum during ILAS
on Lane 4. Checksum for Lane 4.
0x0
R
0x42E COMPSUM4_REG
[7:0] LL_FCMP4
Computed checksum on Lane 4.
Computed checksum for Lane 4
(see description for
Register 0x40E).
0x0
R
0x432 LID5_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID5
Received ILAS LID configuration
on Lane 5. Lane identification
for Lane 5.
0x0
R
0x435 CHECKSUM5_REG
[7:0] LL_FCHK5
Received checksum during ILAS
on lane 5. Checksum for Lane 5.
0x0
R
0x436 COMPSUM5_REG
[7:0] LL_FCMP5
Computed checksum on Lane 5.
Computed checksum for Lane 5
(see description for
Register 0x40E).
0x0
R
0x43A LID6_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID6
Received ILAS LID configuration
on Lane 6. Lane identification
for Lane 6.
0x0
R
0x43D CHECKSUM6_REG
[7:0] LL_FCHK6
Received checksum during ILAS
on Lane 6. Checksum for Lane 6.
0x0
R
0x43E COMPSUM6_REG
[7:0] LL_FCMP6
Computed checksum on Lane 6.
Computed checksum for Lane 6
(see description for
Register 0x40E).
0x0
R
0x442 LID7_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID7
Received ILAS LID configuration
on Lane 7. Lane identification
for Lane 7.
0x0
R
0x445 CHECKSUM7_REG
[7:0] LL_FCHK7
Received checksum during ILAS
on Lane 7. Checksum for Lane 7.
0x0
R
0x446 COMPSUM7_REG
[7:0] LL_FCMP7
Computed checksum on Lane 5.
Computed checksum for Lane 7
(see description for
Register 0x40E).
0x0
R



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