AD8065 datasheet(33/68 Pages) AD

33 / 68 page

Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 33 of 68

Synchronous Dual SPI Mode

In synchronous dual SPI mode, similar to dual SPI mode, the SDI/

SDIO0 and SDO/SDIO1 data lines are bidirectional, as shown in

Figure 81. During the data phase, the R/W bit of the instruction

phase defines the direction of the data lines. During the instruction

phase, the data lines are always configured as inputs. In contrast

to dual SPI mode, in synchronous dual SPI mode each SDIO line

serializes the data of one DAC, as shown in Figure 83.

In this mode, the data transferred on the SDIO0 line is loaded

to the register addressed in the instruction phase, while the data

transferred on the SDIO1 line is loaded to the register at the

address given in the instruction phase that is incremented by 3

bytes in precision mode or the address given in the instruction

phase that is incremented by 2 bytes in fast mode.

Synchronous dual SPI mode can only be used to write the

CHx_DAC_16B, CHx_DAC_24B, CHx_INPUT_16B, and CHx_IN-

PUT_24B registers. To write other registers within the secondary

region, classic SPI must be used.

This transfer mode is useful when the controller is made up of two

entities, each one addressing one DAC with a single bit stream, or

when the CPU cannot serialize the data in groups of two bits. This

mode also allows the simultaneous update of both channels without

any time skew when the LDAC signal is not used.

Figure 83. Synchronous Dual SPI Mode

AD8065 Datasheet(PDF) 33 Page - Analog Devices