AD8065 datasheet(51/68 Pages) AD

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Data Sheet

AD3552R

REGISTERS

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Rev. A | 51 of 68

Interface Configuration D Register

Address: 0x14, Reset: 0x04, Name: INTERFACE_CONFIG_D

This register contains miscellaneous configuration bits affecting SPI communication and electrical parameters of digital signals.

Table 33. Bit Descriptions for INTERFACE_CONFIG_D

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

ALERT_ENABLE_PULLUP

ALERT Pin Control. Enable internal 2.5 kΩ pull-up resistor.

0x0

R/W

0 Internal pull-up disabled. An external pull-up is required.

1 Internal pull-up enabled.

RESERVED

Reserved.

0x0

MEM_CRC_EN

Memory CRC Enable. This bit controls the continuous

checking of the primary register set and the ROM memory.

0x0

R/W

0 Memory CRC checking disabled.

1 Memory CRC checking enabled.

[3:2]

SDIO_DRIVE_STRENGTH

SDIO Drive Strength. These two bits allow for the increase in

SDIO drive strength.

0x1

R/W

00 Low SDIO drive strength.

01 Medium low SDIO drive strength.

10 Medium high SDIO drive strength.

11 High SDIO drive strength.

DUAL_SPI_SYNCHRONOUS_EN

Dual SPI Synchronous Enable. This bit controls the dual

synchronous data transfer using one SDIO line for each DAC

stream.

0x0

R/W

0 Dual synchronous mode disabled.

1 Dual synchronous mode enabled.

SPI_CONFIG_DDR

SPI Configuration DDR. This bit controls the use of DDR for

data transfers.

0x0

R/W

0 DDR mode disabled.

1 DDR mode enabled.

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