AD8065 datasheet(61/68 Pages) AD

61 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 61 of 68

Input Register for Channel 0, Fast Mode

Address: 0x33, Reset: 0x0000, Name: CH0_INPUT_16B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

Table 50. Bit Descriptions for CH0_INPUT_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

INPUT_DATA0

Channel 0 Input Data.

0x0

R/W

Input Register for Channel 1, Fast Mode

Address: 0x35, Reset: 0x0000, Name: CH1_INPUT_16B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

Table 51. Bit Descriptions for CH1_INPUT_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

INPUT_DATA1

Channel 1 Input Data.

0x0

R/W

Hardware LDAC Mask Register, Precision Mode

Address: 0x37, Reset: 0x00, Name: HW_LDAC_24B

This register controls the masking of the external LDAC signal to latch data into each of the DAC channels.

Table 52. Bit Descriptions for HW_LDAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

HW_LDAC_MASK_CH1

Hardware LDAC Mask for Channel 1. This bit controls the latching of data

into the DAC register when the LDAC signal is asserted.

0x0

R/W

0 Data is latched in DAC Register 1 when the LDAC pin is asserted.

1 LDAC signal masked for Channel 1. DAC register is not updated when

LDAC is asserted.

HW_LDAC_MASK_CH0

Hardware LDAC Mask for Channel 0. This bit controls the latching of data

into the DAC register when the LDAC signal is asserted.

0x0

R/W

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