AD8065 datasheet(60/68 Pages) AD

60 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 60 of 68

Table 47. Bit Descriptions for CH_SELECT_16B

Bits

Bit Name

Settings

Description

Reset

Access

0 No operation.

1 Copy to corresponding register in Channel 0.

Input Page Register, Fast Mode

Address: 0x30, Reset: 0x0000, Name: INPUT_PAGE_16B

This register is used to write data to one or both DAC input registers according to the configuration of the SEL_CHx bits in the CH_SE-

LECT_16B register.

Table 48. Bit Descriptions for INPUT_PAGE_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

INPUT_PAGE

Input Page Data. Following a write to this register, the DAC code loaded into this register

is copied into the input register of any channels selected in the CH_SELECT_16B

0x0

R/W

Software LDAC Register, Fast Mode

Address: 0x32, Reset: 0x00, Name: SW_LDAC_16B

This register is used to trigger a data transfer between the input registers and the DAC registers. It is the software equivalent of pulsing the

LDAC line low.

Table 49. Bit Descriptions for SW_LDAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

SW_LDAC_CH1

Software LDAC for Channel 1. Setting this bit transfers contents from the

CH1_INPUT_16B register to the CH1_DAC_16B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 1.

SW_LDAC_CH0

Software LDAC for Channel 0. Setting this bit transfers contents from the

CH0_INPUT_16B register to the CH0_DAC_16B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 0.

AD8065 Datasheet(PDF) 60 Page - Analog Devices

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