AD8065 datasheet(64/68 Pages) AD

64 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 64 of 68

Software LDAC Register, Precision Mode

Address: 0x45, Reset: 0x00, Name: SW_LDAC_24B

This register is used to trigger a data transfer between the input registers and the DAC registers. It is the software equivalent of pulsing the

LDAC line low.

Table 58. Bit Descriptions for SW_LDAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

SW_LDAC_CH1

Software LDAC for Channel 1. Setting this bit transfers contents from the

CH1_INPUT_24B register to the CH1_DAC_24B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 1.

SW_LDAC_CH0

Software LDAC for Channel 0. Setting this bit transfers contents from the

CH0_INPUT_24B register to the CH0_DAC_24B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 0.

Input Register for Channel 0, Precision Mode

Address: 0x46, Reset: 0x000000, Name: CH0_INPUT_24B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

Table 59. Bit Descriptions for CH0_INPUT_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

INPUT_DATA0

Channel 0 Input Data.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

AD8065 Datasheet(PDF) 64 Page - Analog Devices

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