AD8065 datasheet(35/68 Pages) AD

35 / 68 page

Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 35 of 68

The register map is divided in two regions, primary and secondary.

The registers related to interface configuration, DAC configuration,

and error flags are comprised in the primary region from Address

0x0 to Address 0x1E. If the QSPI pin is low, this region can only be

accessed in classic SPI mode with or without DDR, regardless of

the value of MULTI_IO_MODE in the TRANSFER_REGISTER.

The registers affecting the output value of the DAC are comprised

in the secondary region from Address 0x28 to Address 0x4B. This

region can be accessed in any of the SPI modes, with or without

DDR.

If the QSPI pin is high, the interface is configured in full quad

SPI mode for any communication to primary or secondary region

registers.

Figure 87. Register Access Modes

SDIO Drive Strength

The driving strength of the SDIO lines on Pins 5, 6, 7 and

8 can be configured to four different levels by setting the

SDIO_DRIVE_STRENGTH bits in the INTERFACE_CONFIG_D

Higher drive strength value corresponds to a faster signal slew rate,

as shown in Figure 88. However, higher slew rate means higher

peak current and higher digital noise in the system. The default

value is medium low strength.

Figure 88. Driving Strength Options

DAC UPDATE MODES

There are several ways to update the DAC outputs, synchronously

or asynchronously, simultaneously, or individually.

A synchronous update occurs when the change of the DAC output

is triggered by an external signal, such as LDAC, which can be

common to many devices. In this case, the controller loads a value

in the input register that is later transferred to the DAC register

on the falling edge of the LDAC signal, causing the simultaneous

update of all VOUT signals.

If the synchronous update is only required in one of the DACs, the

LDAC signal can be masked using the HW_LDAC_MASK_CHx bits

in the HW_LDAC_16B or the HW_LDAC_24B registers depending

on the precision mode.

An asynchronous update occurs when the change of the DAC

output follows an operation on the register set. In this case, the

change is aligned with the SCLK edge that shifts the last register

bit in. The update can be on one DAC or both DACs simultaneously

following the several combinations described in Table 13.

Page mask registers can be used to transfer the same data to

one or both channels, according to the value of the SEL_CHx bits

in the CH_SELECT_16B or CH_SELECT_24B registers. Writing

to the DAC_PAGE register transfers the data to the CHx_DAC

registers and writing to the INPUT_PAGE register transfers the data

to the CHx_INPUT registers. The data flow between registers is

summarized in Figure 89.

CHx_INPUT

CHx_DAC

INPUT_PAGE

DAC_PAGE

SEL_CHx

HW_LDAC_MASK_CHx

LDAC LOW

LDAC PULSED

Figure 89. DAC Data Flow Between Registers

AD8065 Datasheet(PDF) 35 Page - Analog Devices

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