AD4697 datasheet(104/107 Pages) AD

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Data Sheet

AD4697/AD4698

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Rev. 0 | 104 of 107

Analog Input Settings Configuration Register

Address: 0x0030 to Address 0x0037 (Increments of 0x0001), Reset: 0x08, Name: CONFIG_INn

Table 54. Bit Descriptions for CONFIG_INn

Bits

Bit Name

Description

Reset

Access

TD_EN

INn Threshold Detection Enable Bit. When the standard sequencer is enabled, the TD_EN bit in the CONFIG_IN0

in each CONFIG_INn register enables or disables threshold detection only for its corresponding INn analog input. The

HI_INn and LO_INn alert indicator bits are active when threshold detection is enabled on the corresponding INn analog

input (see the Threshold Detection and Alert Indicators section).

0x0

R/W

0: disables threshold detection for INn.

1: enables threshold detection for INn.

IN_MODE

INn Polarity Mode Select Bit. This bit selects the polarity mode for the corresponding INn analog input (see the Channel

Configuration Options section). Unlike the other control bits in the CONFIG_INn registers, the polarity mode for each

INn analog input is always set by the IN_MODE bit in its corresponding CONFIG_INn register, regardless of the channel

sequencing mode.

0x0

R/W

0: selects unipolar mode for INn.

1: selects pseudobipolar mode for INn.

[5:4]

IN_PAIR

INn Pin-Pairing Select. This field selects the pin-pairing option for the corresponding INn analog input (see the Channel

Configuration Options section). When the standard sequencer is enabled, the IN_PAIR bit field in the CONFIG_IN0

CONFIG_INn register sets the pin-pairing option only for its corresponding INn analog input.

0x0

R/W

0x0: INn paired with REFGND.

0x1: INn paired with COM.

0x2: even and odd input paired.

0x3: invalid.

AINHIZ_EN

INn Analog Input High-Z Mode Enable Bit. When the standard sequencer is enabled, the AINHIZ_EN bit in the

CONFIG_IN0 register enables or disables analog input high-Z mode for IN0 to IN7. When the advanced sequencer is

enabled, the AINHIZ_EN bit in each CONFIG_INn register enables or disables analog input high-Z mode only for its

corresponding INn analog input (see the Analog Input High-Z Mode section).

0x1

R/W

0: disables analog input high-Z mode for INn.

1: enables analog input high-Z mode for INn.

RESERVED

Reserved.

0x0

[1:0]

OSR_SET

INn Oversampling Ratio Select. When the standard sequencer is enabled, the OSR_SET bit field in the CONFIG_IN0

CONFIG_INn register sets the OSR only for its corresponding INn analog input. Set the OSR_SET bit fields in all

CONFIG_INn registers to 0x0 when two-cycle command mode or single-cycle command mode are enabled (see the

Oversampling and Decimation section).

0x0

R/W

0x0: OSR = 1 (no oversampling).

0x1: OSR = 4. Output code result resolution increases to 17 bits.

0x2: OSR = 16. Output code result resolution increases to 18 bits.

0x3: OSR = 64. Output code result resolution increases to 19 bits.

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