WM8581 datasheet(50/94 Pages) WOLFSON

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WM8581

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PP Rev 1.0 March 2006

POSTSCALE_A

PLLACLK FREQUENCY

256fs

128fs

Table 43 PLL S/PDIF Receiver Mode Clock Divider Configuration

PLL CONFIGURATION EXAMPLE

Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the

required PLLBCLK frequency is 12.288MHz.

Calculate the f2, FREQMODE_B and POSTSCALE_B Values

The PLL is designed to operate with best performance when the f2 clock is between 90 and 100MHz. The

necessary PLLBCLK frequency is 12.288MHz. Choose POSTSCALE_B and FREQMODE_B values to set

the f2 frequency in the range of 90 to 100MHz. In this case, the default values (POSTSCALE_B = 0 and

FREQMODE_B[1:0] = 10) will configure the f2 to PLLBCLK divider as 8 and hence will set the f2 frequency at

98.304MHz; this value is within the 90 to 100MHz range and is hence acceptable.

•

POSTSCALE_B = 0

•

FREQMODE_B [1:0] = 10b

•

f2 = 98.304MHz

Calculate R Value

Using the relationship: R = (f2 ÷ f1), the value of R can be calculated.

•

R = (f2 ÷ f1)

•

R = (98.304 ÷ 12)

•

R = 8.192

Calculate PLLB_N Value

The value of PLLB_N is the integer (whole number) value of R, ignoring all digits to the right of the decimal

point. In this case, R is 8.192, hence PLLB_N is 8.

Calculate PLL_K Value

The PLLB_K value is simply the integer value of (2

22 (R-PLLB_N)).

•

PLLB_K = integer part of (2

22 x (8.192 – 8))

•

PLLB_K = integer part of 805306.368

•

PLLB_K = 805306 (decimal) / C49BA (hex)

A number of example configurations are shown in Table 44. Many other configurations are possible; Table 44

shows only a small number of valid possibilities. As both PLLs are identical, the same configuration

procedure applies for both.

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