WM8581 datasheet(75/94 Pages) WOLFSON

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WM8581

PP Rev 1.0 March 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:0

PLLB_K[21:18]

1101

PLLB 3

06h

7:4

PLLB_N[3:0]

0111

Integer (N) divisor part of PLLB input/output frequency ratio. Use

values greater than 5, less than 13.

PRESCALE_B

0 = no pre-scale

1 = divide MCLK by 2 prior to PLLB

POSTSCALE_B

0 = no post scale

1= divide MCLK by 2 after PLLB

FRACEN_B

0 = Integer N PLLB

1 = Fractional K PLLB

4:3

FREQMODE_B

[1:0]

Range Selector for PLLBCLK

(not valid when TXSRC=00)

00 = 192KHz

01 = 88.2KHz to 96KHz

10 = 44.1KHz to 48KHz

11 = 32KHz

6:5

MCLKOUTSRC

MCLK pin output source

00 = MCLK pin configured as an input. The system should be

powered down before changing from this register setting.

01 = PLLACLK

10 = PLLBCLK

11 = OSCCLK

PLLB 4

07h

8:7

CLKOUTSRC

CLKOUT pin source

00 = no output (tristate)

01 = PLLACLK

10 = PLLBCLK

11 = OSCCLK

1:0

DAC_CLKSEL

DAC clock source

00 = MCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

3:2

ADC_CLKSEL

ADC clock source

00 = ADCMLCK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

CLKSEL

08h

5:4

TX_CLKSEL

S/PDIF Transmitter clock source

00 = ADCMLCK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

PAIF 1

09h

2:0

PAIFRX_RATE

[2:0]

010

Master Mode LRCLK Rate

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

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