WM8581 datasheet(67/94 Pages) WOLFSON

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WM8581

PP Rev 1.0 March 2006

PLLBPD

0 = PLLB enabled

1 = PLLB disabled

SPDIFPD

S/PDIF Clock Recovery

PowerDown

0 = S/PDIF enabled

1 = S/PDIF disabled

SPDIFTXD

S/PDIF Transmitter powerdown

0 = S/PDIF Transmitter enabled

1 = S/PDIF Transmitter disabled

SPDIFRXD

S/PDIF Receiver powerdown

0 = S/PDIF Receiver enabled

1 = S/PDIF Receiver disabled

Table 66 Powerdown Registers

INTERNAL POWER ON RESET CIRCUIT

Figure 33 Internal Power On Reset Circuit Schematic

The WM8581 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a

default state after power up.

Figure 33 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The circuit

monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum threshold

Vpor_off.

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until AVDD,

DVDD and VMID voltages have risen above their reset thresholds. When these three conditions have been

met, PORB is released high. When PORB is released high, all registers are in their default state and writes

to the digital interface may take place.

On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum threshold

Vpor_off.

If AVDD is removed at any time, the internal Power On Reset circuit is powered down and the PORB output

will follow the AVDD voltage.

In most applications, the time required for the device to release PORB high will be determined by the charge

time of the VMID node.

WM8581 Datasheet(PDF) 67 Page - Wolfson Microelectronics plc