WM8581 datasheet(66/94 Pages) WOLFSON

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WM8581

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PP Rev 1.0 March 2006

R41

GPO4

29h

3:0

GPO7OP[3:0]

0110

1001 = REC_FREQ192

1010 = ZFLAG

1011 = NON_AUDIO

1100 = CPY_N

1101 = DEEMP

1110 = Set GPO as S/PDIF input (CMOS-compatible

input). Only applicable for GPO3/4/5.

1111 = Set GPO as S/PDIF input (‘comparator’ input for

AC coupled consumer S/PDIF signals). Only applicable

for GPO3/4/5

Table 65 GPO Control Registers

POWERDOWN MODES

The WM8581 has powerdown control bits allowing specific parts of the chip to be turned off when not in use.

The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate

powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use.

DACPD can be overwritten by setting ALLDACPD to powerdown all DACs

The S/PDIF transmitter is powered down by setting SPDIFTXD. Setting SPDIFRXD powers down the S/PDIF

receiver.

The PLL, Oscillator and S/PDIF clock recovery circuits are powered down by setting PLLPD, OSCPD and

SPDIFPD respectively.

Setting all of ADCPD, DACPD[2:0], SPDIFTXD, SPDIFRXD and OUTPD[3:0] will powerdown everything

except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PWDN.

Setting PWDN will override all other powerdown control bits. It is recommended that the ADC and DAC are

powered down before setting PWDN. The default is for all powerdown bits to be set except OSCPD and

PWDN.

BIT

LABEL

DEFAULT

DESCRIPTION

PWDN

Master powerdown (overrides all

powerdown registers)

0 = All digital circuits running,

outputs are active

1 = All digital circuits in power

down mode, outputs muted

ADCPD

ADC powerdown

0 = ADC enabled

1 = ADC disabled

4:2

DACPD[2:0]

111

DAC powerdowns

0 = DAC enabled

1 = DAC disabled

DACPD[0] = DAC1

DACPD[1] = DAC2

DACPD[2] = DAC3

R50

PWRDN 1

32h

ALLDACPD

Overrides DACPD[3:0]

0 = DACs under control of

DACPD[3:0]

1= All DACs are disabled.

OSCPD

OSC output powerdown

0 = OSC output enabled

1 = OSC output disabled

A CMOS input can be applied to

the OSC input when powered

down.

R51

PWRDN 2

33h

PLLAPD

0 = PLLA enabled

1 = PLLA disabled

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