NXP Semiconductors

16

MR2001V

Figure 7. Typical SPI timing chart

6.2

External address solder balls ADR0 and ADR1

To minimize the effort on hardware wiring of signals, the MR2001V uses a combination of hardware and software coded addressing of

each individual chip. Due to this procedure the hardware SEB (chip select) signal usage can be minimized.

If the software addressing is not longer sufficient (e.g. more than 4 RX chips) than a combination of SEB and software addressing is

recommended.

Depending on the chip up to two external solder balls (address bit) are available (ADR0, ADR1). A connection to VCC represents a logical

"1" and a connection to GND represents a logical "0", respectively. By default the logical "1" is already activated by a connection on the

Die. If the corresponding pin is not connected to GND (used ball, not soldered ball), then this represents a logical "1".

Figure 8. External connection of address pins ADR0 and ADR1 to define the identification key of the chip