5

NXP Semiconductors

MR2001V

3

Pin connections

3.1

Pinout diagram

The layout and arrangement of the signal pads are shown in Figure 3.

Figure 3. MR2001V pinout (ball) diagram

3.2

Pin definitions (ball)

A functional description of each pin for the MR2001V can be found in Table 2. Equivalent I/O schematics is found in Table 3

Table 2. MR2001V pin definitions

Ball location

Pin name

Pin function

Pin type

Level

Description

A1, B2, B3, B4, B10, C4, C8, C9,

D4, E3, E4, F5, F6, G9, H7, H9,

J2, J3, J9, K9, L3, L10

GND (4)

DC Ground

Power

0.0 V

A2

RSETB

Digital hard reset signal

Digital Input

0 to 3.3 V

A3

DIVp

Differential Frequency

Divider Output

Analog Output 0 to 3.3 V

A4

DIVn

Differential Frequency

Divider Output

Analog Output 0 to 3.3 V

A5, A7, B5, B7, C5, C7, D5, D6,

D7, D8, D9, D10, E7, F1, F2, F3,

F4, F7, F8, F9, F10, G4, H1, H2,

H3, H4, H5, H6, J4, J6, K4, K6,

L4, L6

GND1 (4)

RF Ground

Power

0.0 V

A8, A9, A10, B8, B9, K1, K2, K3,

L1, L2

VCC1 (3)

3.3 V Power Supply

Power

3.3 V

B1

TREG

1.8 V Regulator Output Analog Output 0 to 3.3 V

C1

SEB

SPI enable (chip

enable)

Digital Input

0 to 3.3 V

C10

SCANB

Digital scan test

Digital Input

0 to 3.3 V

Transparent Top View

A

B

C

D

E

F

G

H

J

K

L

12

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