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MR2001V Datasheet(PDF) 21 Page - NXP Semiconductors |
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MR2001V Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 40 page ![]() 21 NXP Semiconductors MR2001V 7.2.4 0x03 VCO enable and LO input peak detector bits 7.2.5 0x04 VCO LO1 control register Address 0x03 Access: user read write Bit 76543210 R/W LO4 LO3 LO2 LO1 DIV_OUT VC0_BUFEN RESERVED RESERVED Reset 00000000 Field R/W Description [1:0] RESERVED Reserved bits [2] VC0_BUFEN Enable VCO buffer [3] DIV_OUT Enable last 5 divder stages [4] LO1 Enable LO output 1. LOPWR_ch1 need to be set different from 0 prior to LO1 activation [5] LO2 Enable LO output 2. LOPWR_ch2 need to be set different from 0 prior to LO2 activation [6] LO3 Enable LO output 3. LOPWR_ch3 need to be set different from 0 prior to LO3 activation [7] LO4 Enable LO output 4. LOPWR_ch4 need to be set different from 0 prior to LO4 activation Address 0x04 Access: user read write Bit 7 6543210 R/W NOT_USED NOT_USED LOPWR4_ch1 LOPWR3_ch1 LOPWR2_ch1 LOPWR1_ch1 RESERVED RESERVED Reset 0 0000000 Field R/W Description [1:0] RESERVED Reserved bits [7:6] NOT_USED Unused bits Field [5] Field [4] Field [3] Field [2] LO1 output power level: 0 0 0 0 No current to output stage; highest possible attenuation 0 0 0 1 Approx. 10.5 dB attenuation, POUT ~ -7.0 dBm 0 010 -4.0 dBm > POUT > -7.0 dBm 0 0 1 1 Approx. 7.0 dB attenuation, POUT ~ -4.0 dBm 0 1 0 0 0 dBm > POUT > -4.0 dBm 0 1 0 1 0 dBm > POUT > -4.0 dBm 0 1 1 0 0 dBm > POUT > -4.0 dBm 0 1 1 1 Approx. 3.5 dB attenuation, POUT ~ 0 dBm 1 0 0 0 3.0 dBm > POUT > 0 dBm 1 0 0 1 3.0 dBm > POUT > 0 dBm |
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