NXP Semiconductors

6

MR2001V

C6

LO4

38 GHz LO output

channel 4

RF Output

0 V

D2

SCLK

SPI serial clock

Digital Input

0 to 3.3 V

E1

MISO

SPI MISO (master in,

slave out)

Digital Output

0 to 3.3 V

E2

MOSI

SPI MOSI (master out,

slave in)

Digital Input

0 to 3.3 V

E8

LO3

38 GHz LO output

channel 3

RF Output

0 V

G10

RP

Bandgap reference

resistor (positive

temperature slope)

Analog Input

0 to 3.3 V

See Table 6

G3

LO1

38 GHz LO output

channel 1

RF Output

0 V

H10

RN

Bandgap reference

resistor (negative

temperature slope)

Analog Input

0 to 3.3 V

See Table 6

J1

TEST

Output to monitor

internal bias nodes via

ASCAN

Analog Output 0 to 3.3 V

J10

VVCO

4.5 V Power Supply

(only for the VCO core)

Power

4.5 V

J5

LO2

38 GHz LO output

channel 2

RF Output

0 V

J7, K7, K8, L8, L9

VCC2 (3)

3.3 V Power Supply

Power

3.3 V

K10

VTUNE

Tuning Voltage

Analog Input

0 to 4.5 V

L7

SENS

Sensor output

(temperature and

power peak detector)

Analog output 0 to 3.3 V

Notes

3.

VCC1, VCC2, VCC3 are only connected via the on-chip metal layers. It is mandatory for each supply domain to be connected to the common

power supply.

4.

GND and GND1 are connected together in the package via the interconnection layer. GND1 is mandatory to be connected, to realize a suitable

RF PCB to package transition.

Table 2. MR2001V pin definitions (continued)

Ball location

Pin name

Pin function

Pin type

Level

Description