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MPC850EC Datasheet(PDF) 36 Page - NXP Semiconductors |
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MPC850EC Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 36 Freescale Semiconductor Bus Signal Timing Table 10 shows the debug port timing for the MPC850. Figure 29 provides the input timing for the debug port clock. Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. Figure 30. Debug Port Timings Table 10. Debug Port Timing Num Characteristic 50 MHz 66 MHz 80 MHz Unit Min Max Min Max Min Max D61 DSCK cycle time 60.00 — 91.00 — 75.00 — ns D62 DSCK clock pulse width 25.00 — 38.00 — 31.00 — ns D63 DSCK rise and fall times 0.00 3.00 0.00 3.00 0.00 3.00 ns D64 DSDI input data setup time 8.00 — 8.00 — 8.00 — ns D65 DSDI data hold time 5.00 — 5.00 — 5.00 — ns D66 DSCK low to DSDO data valid 0.00 15.00 0.00 15.00 0.00 15.00 ns D67 DSCK low to DSDO invalid 0.00 2.00 0.00 2.00 0.00 2.00 ns DSCK D61 D63 D62 D62 D63 DSCK DSDI DSDO D64 D65 D66 D67 |
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