MPC850EC datasheet(46/72 Pages) NXP

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Figure 44. CPM General-Purpose Timers Timing Diagram

8.5

Serial Interface AC Electrical Specifications

Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49.

Table 17. SI Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

L1RCLK, L1TCLK frequency (DSC = 0) 1, 2

—

SYNCCLK/2.

MHz

L1RCLK, L1TCLK width low (DSC = 0) 2

P + 10

—

71a

L1RCLK, L1TCLK width high (DSC = 0) 3

P + 10

—

L1TXD, L1ST

n, L1RQ, L1xCLKO rise/fall time

—

15.00

L1RSYNC, L1TSYNC valid to L1xCLK edge Edge

(SYNC setup time)

20.00

—

L1xCLK edge to L1RSYNC, L1TSYNC, invalid

(SYNC hold time)

35.00

—

L1RSYNC, L1TSYNC rise/fall time

—

15.00

L1RXD valid to L1xCLK edge (L1RXD setup time)

17.00

—

L1xCLK edge to L1RXD invalid (L1RXD hold time)

13.00

—

L1xCLK edge to L1ST

n valid 4

10.00

45.00

78A

L1SYNC valid to L1ST

n valid

10.00

45.00

L1xCLK edge to L1ST

n invalid

10.00

45.00

L1xCLK edge to L1TXD valid

10.00

55.00

80A

L1TSYNC valid to L1TXD valid 4

10.00

55.00

L1xCLK edge to L1TXD high impedance

0.00

42.00

CLKOUT

TIN/TGATE

(Input)

TOUT

(Output)

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