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MMPF0200 Datasheet(PDF) 95 Page - NXP Semiconductors |
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MMPF0200 Datasheet(HTML) 95 Page - NXP Semiconductors |
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95 / 115 page ![]() NXP Semiconductors 95 PF0200 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS D8 OTP VGEN5 VOLT R/W 8'b0000_xxxx –– – – VGEN5_VOLT[3:0] 00 0 0 x x x x D9 OTP VGEN5 SEQ R/W 8'b000x_xxxx –– – VGEN5_SEQ[4:0] 00 0 x x x x x DC OTP VGEN6 VOLT R/W 8'b0000_xxxx –– – – VGEN6_VOLT[3:0] 00 0 0 x x x x DD OTP VGEN6 SEQ R/W 8'b000x_xxxx –– – VGEN6_SEQ[4:0] 00 0 x x x x x E0 OTP PU CONFIG1 R/W 8'b000x_xxxx –– – PWRON_ CFG1 SWDVS_CLK1[1:0] SEQ_CLK_SPEED1[1:0] 00 0 x x x x x E1 OTP PU CONFIG2 R/W 8'b000x_xxxx –– – PWRON_ CFG2 SWDVS_CLK2[1:0] SEQ_CLK_SPEED2[1:0] 00 0 x x x x x E2 OTP PU CONFIG3 R/W 8'b000x_xxxx –– – PWRON_ CFG3 SWDVS_CLK3[1:0] SEQ_CLK_SPEED3[1:0] 00 0 x x x x x E3 OTP PU CONFIG XOR R 8'b000x_xxxx –– – PWRON_CFG _XOR SWDVS_CLK3_XOR SEQ_CLK_SPEED_XOR 00 0 x x x x x E4(76) OTP FUSE POR1 R/W 8'b0000_00x0 TBB_POR SOFT_FUSE_ POR –– – – FUSE_POR1 – 00 0 0 0 0 x0 E5(76) OTP FUSE POR1 R/W 8'b0000_00x0 RSVD RSVD – – – – FUSE_POR2 – 00 0 0 0 0 x0 E6(76) OTP FUSE POR1 R/W 8'b0000_00x0 RSVD RSVD – – – – FUSE_POR3 – 00 0 0 0 0 x0 E7 OTP FUSE POR XOR R 8'b0000_00x0 RSVD RSVD – – – – FUSE_POR_X OR – 00 0 0 0 0 x0 E8 OTP PWRGD EN R/W/M 8'b0000_000x –– – – – – – OTP_PG_EN 00 0 0 0 0 x0 F0 OTP EN ECCO R/W 8'b000x_xxxx –– – EN_ECC_ BANK5 EN_ECC_ BANK4 EN_ECC_ BANK3 EN_ECC_ BANK2 EN_ECC_ BANK1 00 0 x x x x x F1 OTP EN ECC1 R/W 8'b000x_xxxx –– – EN_ECC_ BANK10 EN_ECC_ BANK9 EN_ECC_ BANK8 EN_ECC_ BANK7 EN_ECC_ BANK6 00 0 x x x x x Table 121. Extended page 1 (continued) Address Register Name TYPE Default BITS[7:0] 7 6 5 4 3 2 1 0 |
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