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TUSB1004 Datasheet(PDF) 29 Page - Texas Instruments

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Part # TUSB1004
Description  TUSB1004 USB 3.2 10 Gbps Quad-Channel Adaptive Linear Redriver
PDF  53 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TUSB1004 Datasheet(HTML) 29 Page - Texas Instruments

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7.5.3 TUSB1004 I2C Target Behavior
A6
A5
A4
A3
A2
A1
A0
0
S
C7
C6
C5
C4
C3
C2
C1
C0
A
Target Address
A
Register O set
Write
Ack
Start
D7
D6
D5
D4
D3
D2
D1
D0
A
Data wri en
Figure 7-2. I2C Write with Data
The following procedure should be followed to write data to TUSB1004 I2C registers (refer to Figure 7-2):
1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1004 acknowledges the address cycle.
3. The controller presents the register offset within TUSB1004 to be written, consisting of one byte of data,
MSB-first.
4. The TUSB1004 acknowledges the sub-address cycle.
5. The controller presents the first byte of data to be written to the I2C register.
6. The TUSB1004 acknowledges the byte transfer.
7. The controller may continue presenting additional bytes of data to be written, with each byte transfer
completing with an acknowledge from the TUSB1004.
8. The controller terminates the write operation by generating a stop condition (P).
A6
A5
A4
A3
A2
A1
A0
1
S
D7
D6
D5
D4
D3
D2
D1
D0
A
Target Address
A
P
Data from o set 0x00
or
last read address + 1
Read
Ack
Start
Stop
Figure 7-3. I2C Read Without Repeated Start
The following procedure should be followed to read the TUSB1004 I2C registers without a repeated Start (refer
Figure 7-3).
1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1004 7-bit
address and a zero-value “W/R” bit to indicate a read cycle.
2. The TUSB1004 acknowledges the 7-bit address cycle.
3. Following the acknowledge the controller continues sending clock.
4. The TUSB1004 transmit the contents of the memory registers MSB-first starting at register 00h or last read
register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB1004 shall start at the
register offset specified in the write.
5. The TUSB1004 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB1004 transmits the next byte of data as long as controller provides the clock.
If a NAK is received, the TUSB1004 stops providing data and waits for a stop condition (P).
7. The controller terminates the write operation by generating a stop condition (P).
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TUSB1004
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