CS47L85 datasheet(105/370 Pages) CIRRUS

105 / 370 page

CS47L85

Rev 4.3

105

4-input mixer is associated with each PWM generator, as illustrated in Figure 36.

When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the duty

cycle ratio is configurable using the PWMn_LVL registers.

The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, this register should be set

to the highest available setting. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK (if

PWM_RATE<1000) or ASYNCCLK (if PWM_RATE

≥1000).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R48 (0030h)

PWM_Drive

10:8

PWM_CLK_SEL

[2:0]

000

PWM Clock Select

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only.

PWM_CLK_SEL controls the resolution

of the PWM generator; higher settings

correspond to higher resolution.

The PWM Clock must be less than or

equal to SYSCLK (if PWM_RATE<1000)

or less than or equal to ASYNCCLK (if

PWM_RATE>=1000).

PWM2_OVD

PWM2 Generator Override

0 = Disabled (PWM duty cycle is

controlled by audio source)

1 = Enabled (PWM duty cycle is

controlled by PWM2_LVL).

PWM1_OVD

PWM1 Generator Override

0 = Disabled (PWM1 duty cycle is

controlled by audio source)

1 = Enabled (PWM1 duty cycle is

controlled by PWM1_LVL).

PWM2_ENA

PWM2 Generator Enable

0 = Disabled

1 = Enabled

PWM1_ENA

PWM1 Generator Enable

0 = Disabled

1 = Enabled

R49 (0031h)

PWM_Drive

9:0

PWM1_LVL [9:0]

100h

PWM1 Override Level

Sets the PWM1 duty cycle when

PWM1_OVD=1.

Coded as 2’s complement.

000h = 50% duty cycle

200h = 0% duty cycle

R50 (0032h)

PWM_Drive

9:0

PWM2_LVL [9:0]

100h

PWM2 Override Level

Sets the PWM2 duty cycle when

PWM2_OVD=1.

Coded as

2’s complement.

000h = 50% duty cycle

200h = 0% duty cycle

Table 21 Pulse Width Modulation (PWM) Generator Control

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the digital mixer

paths. If an attempt is made to enable a PWM signal mixer path, and there are insufficient SYSCLK cycles to support it, then

the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

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