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CS47L85 Datasheet(PDF) 180 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 180 Page - Cirrus Logic

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CS47L85
180
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
AIF3RX1_ENA
0
AIF3 Audio Interface RX Channel 1
Enable
0 = Disabled
1 = Enabled
Table 43 AIF3 Signal Path Enable
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1465
(05B9h)
AIF4_Tx_
Enables
1
AIF4TX2_ENA
0
AIF4 Audio Interface TX Channel 2
Enable
0 = Disabled
1 = Enabled
0
AIF4TX1_ENA
0
AIF4 Audio Interface TX Channel 1
Enable
0 = Disabled
1 = Enabled
R1466
(05BAh)
AIF4_Rx_
Enables
1
AIF4RX2_ENA
0
AIF4 Audio Interface RX Channel 2
Enable
0 = Disabled
1 = Enabled
0
AIF4RX1_ENA
0
AIF4 Audio Interface RX Channel 1
Enable
0 = Disabled
1 = Enabled
Table 44 AIF4 Signal Path Enable
AIF BCLK AND LRCLK CONTROL
The AIFnBCLK frequency is selected by the AIFn_BCLK_FREQ register. For each value of this register, the actual frequency
depends upon whether AIFn is configured for a 48kHz-related sample rate or a 44.1kHz-related sample rate, as described
below.
If AIFn_RATE<1000 (see Table 22), then AIFn is referenced to the SYSCLK clocking domain and the applicable frequency
depends upon the SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3 registers.
If AIFn_RATE
≥1000, then AIFn is referenced to the ASYNCCLK clocking domain and the applicable frequency depends
upon the ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2 registers.
The selected AIFnBCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable.
See “Clocking and
Sample Rates
” for details of SYSCLK and ASYNCCLK domains, and the associated control registers.
The AIFnLRCLK frequency is controlled relative to AIFnBCLK by the AIFn_BCPF divider.
Note that the BCLK rate must be configured in Master or Slave modes, using the AIFn_BCLK_FREQ registers. The LRCLK
rate(s) only require to be configured in Master mode.



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