CS47L85 datasheet(177/370 Pages) CIRRUS

177 / 370 page

CS47L85

Rev 4.3

177

AIF SIGNAL PATH ENABLE

The AIF1 and AIF2 interfaces support up to 8 input (RX) channels and up to 8 output (TX) channels. Each of these channels

can be enabled or disabled using the register bits defined in Table 41 and Table 42.

The AIF3 and AIF4 interfaces support up to 2 input (RX) channels and up to 2 output (TX) channels. Each of these channels

can be enabled or disabled using the register bits defined in Table 43 and Table 44.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The AIF signal paths should

be kept disabled (AIFnTXm_ENA=0, AIFnRXm_ENA=0) if SYSCLK is not enabled. The ASYNCCLK may also be required,

depending on the path configuration. See “Clocking and Sample Rates” for details of the system clocks (including

requirements for reconfiguring SYSCLK while audio paths are enabled).

The audio interfaces can be re-configured whilst enabled, including changes to the LRCLK frame length and the channel

timeslot configurations. Care is required to ensure that this ‘on-the-fly’ re-configuration does not cause corruption to the

active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.

As noted in the applicable register descriptions, some of the AIF control fields are locked and cannot be updated whilst AIF

channels are enabled; this is to ensure continuity of the respective BCLK and LRCLK signals.

The CS47L85 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enough to

support the commanded signal paths and processing functions. If an attempt is made to enable an AIF signal path, and

there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any

signal paths that are already active will not be affected under these circumstances.)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1305

(0519h)

AIF1_Tx_

Enables

AIF1TX8_ENA

AIF1 Audio Interface TX Channel 8

Enable

0 = Disabled

1 = Enabled

AIF1TX7_ENA

AIF1 Audio Interface TX Channel 7

Enable

0 = Disabled

1 = Enabled

AIF1TX6_ENA

AIF1 Audio Interface TX Channel 6

Enable

0 = Disabled

1 = Enabled

AIF1TX5_ENA

AIF1 Audio Interface TX Channel 5

Enable

0 = Disabled

1 = Enabled

AIF1TX4_ENA

AIF1 Audio Interface TX Channel 4

Enable

0 = Disabled

1 = Enabled

AIF1TX3_ENA

AIF1 Audio Interface TX Channel 3

Enable

0 = Disabled

1 = Enabled

AIF1TX2_ENA

AIF1 Audio Interface TX Channel 2

Enable

0 = Disabled

1 = Enabled

AIF1TX1_ENA

AIF1 Audio Interface TX Channel 1

Enable

0 = Disabled

1 = Enabled

R1306

(051Ah)

AIF1_Rx_

Enables

AIF1RX8_ENA

AIF1 Audio Interface RX Channel 8

Enable

0 = Disabled

1 = Enabled

CS47L85 Datasheet(PDF) 177 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 177 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL