CS47L85 datasheet(173/370 Pages) CIRRUS

173 / 370 page

CS47L85

Rev 4.3

173

DIGITAL AUDIO INTERFACE CONTROL

This section describes the configuration of the CS47L85 digital audio interface paths.

AIF1 and AIF2 support up to 8 input signal paths and up to 8 output signal paths; AIF3 and AIF4 support up to 2 channels

of input and output signal paths. The digital audio interfaces can be configured as Master or Slave interfaces; mixed

master/slave configurations are also possible.

Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input (RX) paths

use shared BCLK and LRCLK control signals.

The digital audio interface supports flexible data formats, selectable word-length, configurable timeslot allocations and TDM

tri-state control.

The audio interfaces can be re-configured whilst enabled, including changes to the LRCLK frame length and the channel

timeslot configurations. Care is required to ensure that any ‘on-the-fly’ re-configuration does not cause corruption to the

active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.

As noted in the applicable register descriptions, some of the AIF control fields are locked and cannot be updated whilst AIF

channels are enabled; this is to ensure continuity of the respective BCLK and LRCLK signals.

AIF SAMPLE RATE CONTROL

The AIF RX inputs may be selected as input to the digital mixers or signal processing functions within the CS47L85 digital

core. The AIF TX outputs are derived from the respective output mixers.

The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE register - see Table 22

within the “Digital Core” section.

Note that sample rate conversion is required when routing the AIF paths to any signal chain that is asynchronous and/or

configured for a different sample rate.

AIF PIN CONFIGURATION

The external connections associated with each digital audio interface (AIF) are implemented on multi-function GPIO pins,

which must be configured for the respective AIF functions when required. The AIF connections are pin-specific alternative

functions available on specific GPIO pins. See “General Purpose Input / Output” to configure the GPIO pins for AIF operation.

Integrated pull-up and pull-down resistors can be enabled on the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This is

provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices.

Each of the pull-up and pull-down resistors can be configured independently using the register bits described in Table 94.

When the pull-up and pull-down resistors are both enabled, the CS47L85

provides a ‘bus keeper’ function on the respective

pin. The bus keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tri-stated).

CS47L85 Datasheet(PDF) 173 Page - Cirrus Logic