CS47L85 datasheet(169/370 Pages) CIRRUS

169 / 370 page

CS47L85

Rev 4.3

169

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

RXDAT/

TXDAT

Figure 52 Left Justified Data Format (assuming n-bit word length)

AIF TIMESLOT CONFIGURATION

Digital audio interfaces AIF1 and AIF2 support multi-channel operation, with up to 8 channels of input and output in each

case. A high degree of flexibility is provided to define the position of the audio samples within each LRCLK frame; the audio

channel samples may be arranged in any order within the frame.

AIF3 and AIF4 also provide flexible configuration options, but these interfaces support only 1 stereo input and 1 stereo

output path.

Note that, on each interface, all input and output channels must operate at the same sample rate (fs).

Each of the audio channels can be enabled or disabled independently on the transmit (TX) and receive (RX) signal paths.

For each enabled channel, the audio samples are assigned to one timeslot within the LRCLK frame.

In DSP modes, the timeslots are ordered consecutively from the start of the LRCLK frame. In I2S and Left-Justified modes,

the even-numbered timeslots are arranged in the first half of the LRCLK frame, and the odd-numbered timeslots are arranged

in the second half of the frame.

The timeslots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is no requirement to

assign every available timeslot to an audio sample; some slots may be unused, if desired. Care is required, however, to

ensure that no timeslot is allocated to more than one audio channel.

The number of BCLK cycles within a slot is configurable; this is the Slot Length. The number of valid data bits within a slot

is also configurable; this is the Word Length. The number of BCLK cycles per LRCLK frame must be configured; it must be

ensured that there are enough BCLK cycles within each LRCLK frame to transmit or receive all of the enabled audio channels.

Examples of the AIF Timeslot Configurations are illustrated in Figure 53 to Figure 56. One example is shown for each of the

four possible data formats.

Figure 53 shows an example of DSP Mode A format. Four enabled audio channels are shown, allocated to timeslots 0

through to 3.

LRCLK

Slot 0

Slot 1

Slot 2

Slot 3

Slot 4

Slot 5

Slot 6

Slot 7

...

Slot 0

Slot 3

AIF1[TX1/RX1]_SLOT = 0

Channel 1

Channel 2

Channel 3

Channel 4

BCLK

TXDAT/

RXDAT

Slot 1

Slot 2

AIF1[TX2/RX2]_SLOT = 1

AIF1[TX3/RX3]_SLOT = 2

AIF1[TX4/RX4]_SLOT = 3

Figure 53 DSP Mode A Example

CS47L85 Datasheet(PDF) 169 Page - Cirrus Logic

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