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CS47L85 Datasheet(PDF) 166 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 166 Page - Cirrus Logic

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CS47L85
166
Rev 4.3
DIGITAL AUDIO INTERFACE
The CS47L85 provides four audio interfaces, AIF1, AIF2, AIF3 and AIF4. Each of these is independently configurable on
the respective transmit (TX) and receive (RX) paths. AIF1 and AIF2 support up to 8 channels of input and output signal
paths; AIF3 and AIF4 support up to 2 channels of input and output signal paths.
The data source(s) for the audio interface transmit (TX) paths can be selected from any of the CS47L85 input signal paths,
or from the digital core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of the
digital core processing functions or digital core outputs. See “Digital Core” for details of the digital core routing options.
The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical connections
include Applications Processor, Baseband Processor and Wireless Transceiver. Note that the SLIMbus interface also
provides digital audio input/output paths, providing options for additional interfaces. A typical configuration is illustrated in
Figure 46.
The audio interfaces AIF1 and AIF2 are referenced to DBVDD1 and DBVDD2 respectively; interfaces AIF3 and AIF4 are
referenced to DBVDD3. This enables the CS47L85 to connect easily between application sub-systems on different voltage
domains.
Audio Interface 1
Audio Interface 2
Audio Interface 3
HDMI
Device
Baseband
Processor
Wireless
Transceiver
CS47L85
SLIMbus interface
Applications
Processor
Figure 46 Typical AIF Connections
In the general case, the digital audio interface uses four pins:
TXDAT: Data output
RXDAT: Data input
BCLK: Bit clock, for synchronisation
LRCLK: Left/Right data alignment clock
In master interface mode, the clock signals BCLK and LRCLK are outputs from the CS47L85. In slave mode, these signals
are inputs, as illustrated below.



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