CS47L85 datasheet(167/370 Pages) CIRRUS

167 / 370 page

CS47L85

Rev 4.3

167

Four different audio data formats are supported by the digital audio interface:



DSP mode A



DSP mode B



I2S



Left Justified

The Left Justified and DSP-B modes are valid in Master mode only (i.e., BCLK and LRCLK are outputs from the CS47L85).

These modes cannot be supported in Slave mode.

All four of these modes are MSB first.

Data words are encoded in 2’s complement format. Each of the audio interface modes

described in the following sections. Refer to the “Signal Timing Requirements” section for timing information.

Two variants of DSP mode are supported -

‘Mode A’ and ‘Mode B’. Mono PCM operation can be supported using the DSP

modes.

MASTER AND SLAVE MODE OPERATION

The CS47L85 digital audio interfaces can operate as a master or slave as shown in Figure 47 and Figure 48. The associated

control bits are described in “Digital Audio Interface Control”.

CS47L85

TXDAT

LRCLK

RXDAT

BCLK

Processor

CS47L85

Processor

TXDAT

LRCLK

RXDAT

BCLK

Figure 47 Master Mode

Figure 48 Slave Mode

AUDIO DATA FORMATS

The CS47L85 digital audio interfaces can be configured to operate in I2S, Left-Justified, DSP-A or DSP-B interface modes.

Note that Left-Justified and DSP-B modes are valid in Master mode only (i.e., BCLK and LRCLK are outputs from the

CS47L85).

The digital audio int

erfaces also provide flexibility to support multiple ‘slots’ of audio data within each LRCLK frame. This

flexibility allows multiple audio channels to be supported within a single LRCLK frame.

The data formats described in this section are generic descriptions, assuming only one stereo pair of audio samples per

LRCLK frame. In these cases, the AIF is configured to transmit (or receive) in the first available position in each frame (i.e.,

the Slot 0 position).

The options for multi-channel operation are desc

ribed in the following section (“AIF Timeslot Configuration”).

The audio data modes supported by the CS47L85 are described below. Note that the polarity of the BCLK and LRCLK

signals can be inverted if required; the following descriptions all assume the default, non-inverted polarity of these signals.

In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK following a

rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In master mode, the LRCLK output will resemble the frame pulse shown in Figure 49 and Figure 50. In slave mode, it is

possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs at least one

BCLK period before the rising edge of the next frame pulse.

CS47L85 Datasheet(PDF) 167 Page - Cirrus Logic

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